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High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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This question is further to: How accurate are internal terminators on chips with high speed differential inputs?. I would like to measure the actual termination resistance inside one of these chips (...
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I have a 1.8 V, 350 MHz, 100 Ω LVDS signal on an FFC on the bottom plane. Below the FFC is an aluminum metal layer; the aluminum is pretty much unconnected from the FFC. The air gap/solder mask gap is ...
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This is the first time I am making a high speed PCB so I am a bit unconfident. the ic I am talking about is this: FTDI232H I have followed the schematic in the datasheet above and I have placed the ...
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I'm aware that due to process variation, some analog parameters of semiconductor devices can vary; sometimes quite a lot. (E.g. the SST3904 transistor specifies a DC current gain somewhere between 100 ...
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In a project I'm working on, we're seeing regular frame drops on a 1-lane, 900Mbps MIPI CSI-2 interface. After some investigating, I'm fairly sure that the problem is related to signal integrity. ...
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Given n bits, for example, 00100110110001, there are six 1s in these bits. I want to output 11111100000000, which moves the non-consecutive bit 1s to the left of the string. I know some sequential ...
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I am looking at an open-source design for an NVIDIA Jetson Nano carrier board made by a company called AntMicro. See here The design is an 8-layer design with the following Stack-Up and Build-Up ...
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I need to route DDR4x2(3200MHz) to my FPGA. my stackup is 12 Layers, TH Via only, and thickness of 2mm PCB. my question regard which layer to route the FPGA to DDR4, when the two component on the TOP(...
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I see many people with some knowledge of PCB design, says it is bad practice to run high-speed signals of a "disconnected" ground place adjacent to the signal. But no one shows practically ...
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This question is specifically about PCB layout for high speed memory interface: DDR3, DDR4, DDR5. I can see that often people would use microvias for high speed interfaces. The board I have seen was ...
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I try to connect USB 2.0 to a FTDI FT2232HL. This is my first high speed layout. I am planning to use 2-layer board 1.6 mm. I know that I have to keep 50 Ω Z0 and 90 Ω Zdiff. However with the 2-layer ...
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How can I translate a unidirectional signal from 3.3 V to 1.8 V with a bandwidth of 500 MHz? The signal I am interested in is the output of a high speed comparator (TLV3601) and I have to measure the ...
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I plan to make a high-speed resistive probe according to the book "High-speed digital design: A Handbook of Black Magic". There is one thing I don't understand there: Why this probe (unlike ...
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I was watching a teardown video for a scope and saw that the high speed input circuit has a copper frame around each input. What is the purpose of this and what is it called? It has a heatsink on top ...
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I have ethernet differential signals and a discrete magnetics part. I want to know what issues might arise if I place vias on the differential signals when connecting them between the magnetics and ...
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Most resistors will be metal film (aka thin film) and most capacitors will be ceramic (class II dielectric). Small components have less parasitive inductance than larger ones. There are different type ...
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This is the report generated from Keysight ADS. I can see the reflections from the vias and layer change (impedance swing) but I couldn't figure out the impedance of the actual traces. Also, why are ...
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I am looking to design a SATA adapter board which interfaces an FPGA LPC FMC connector with a SATA connector. This board will contain the 6 signals (RX+, RX-, TX+, TX-, and Clk+, Clk-) along with ...
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Used the SI Power Aware analysis on the DP/DM signals for this simulation: I'm having more issues on my Tx rather than the Rx. I do understand the Rx eye diagram but I'm struggling with the wild ...
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In one of his video Rick Hartley says signals with fast rise time can cause EMI/EMC issues. I am using FS32K148UJT0VLQT in my design. In my board this controller is working at 5 V supply. Below image ...
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I saw these lines in a data sheet: "To reduce unwanted capacitance, TI recommends cutting out the power and ground traces underneath the signal input and output pins. Otherwise, ground and power ...
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In some pcb stackup's I can see that the power plane is given as reference to signal layers. I have some questions regarding this. May I know in that case how the return current flows. Assume all my ...
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I am currently designing a host board for SFP+ modules. My premise is that I have never designed for high speed therefore I looked up online for application notes and sample boards. I have mainly 3 ...
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In my board there are many IC's present and for all these IC's it's manufacturers specified the decoupling capacitors. When I generated my initial BOM what I observed is 99% of these capacitors are of ...
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I need to connect two PCBs together that have components only on the top side. I hoped to connect them with a flex cable mated on the top side of the PCB, like the image below (green are the PCBs, ...
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Using series or parallel termination resistor aims to improve signal integrity by reducing reflections caused by discontinuities in the characteristic impedance. This much is clear. What is not clear ...
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There is a device. On board, STM32F446 + USB3315 as PHY + USB HUB assembled on USB2503. Frequency APB 180 MHz A device project with a CDC interface has been created in CUbeMX. On command from the host,...
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I have a high speed design that runs at 1.6GHz, there are also matched traces on a 12 layer board. Now I would like to know if the design will function over temperature of a -10C to 50C range and if ...
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I am looking to make a 5mm connection from a programmer board to another board with USB 2.0 on it through some pogo pins. Could something like this work for the high speed over a short distance? Any ...
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I need high speed SPI peripherals to control some SK9822 LED's (which can be clocked at up to 30 MHz, which I'd like to use (the speed is needed because of the LEDs being in motion) So I searched for ...
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I am trying to create an xsignal link between processor and a connector to measure the timing (because there are resistors on some of the lines). I don't see the connector in the list (J3, the rest ...
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I am receiving an LVDS clock differential signals and need to convert them to LVTTL . the problem is that the LVDS frequency is above 500Mhz and the LVTTL output needs to drive a 50ohm resistors, when ...
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I know that If the length of the track is between 1/6 or 1/4 of the effective length of a feature like an edge a system can be regarded as lumped. BUT A a lot of times, the rise time cannot be taken ...
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I am learning about PCB stackup from this video. It describes a 10-layer stackup as shown below. Layer 5 and layer 6 are power planes. The author says to prevent power planes referencing each other, ...
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Imagine I have a HDMI bus with differential impedance 100 Ohm and length 10cm Imagine that for a segment of length "L" there is an impedance variation of "DELTA" Question: in order ...
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I have several accordion objects in altium. I need to change the trace width. If the trace is selected it won't show up the properties window to change the width. The only way I have found to change ...
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I'm using this KSZ8041MLLI device and this is its Hardware checklist I'm using the MII Interface between this PHY and the MAC Controller (STM32 MCU) on the same board. My question is whether we ...
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Recently I have started working on a project where want to use a (Zynq Ulteascale+ FPGA) SoM. The device is equipped with fine-pitch mezzanine connectors, over which I want to use the USB3, Ethernet ...
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It's rather easy to find the schematics for a CMOS NAND gate on the net -- two series NMOS transistors as the pull-down network, two parallel PMOS transistors as the pull-up network. What would an ...
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When routing controlled-impedance differential signals (100 MHz) in the middle of a PCB, do the reference planes have to be directly adjacent? If no, is there any issue if there is another signal ...
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I have a 0..5 V digital signal with a minimum pulse width of 200 ns. I would like to measure the pulse width and the time between the rising edges of pulses. In my case it would be enough to measure ...
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I'm working on a device that will have an onboard storage device with a USB interface, as well as two USB 3.0 type-A connectors (a plug and a socket), along with a USB hub ic. I'm using the Microchip ...
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How tightly should trace lengths be matched for a 1Gbps serial databus? It seems to me that 100ps (15mm) should be more than sufficient. However: The Raspberry Pi Computer Module 4 (CM4) datasheet ...
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In the past I have designed a platform that used an Intel Tiger Lake (Gen 11) CPU and now I have a new project that uses the AMD R6000 series. Different from Intel, the design of the DP++ feature ...
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I have a doubt about the PCIe present pin working principle, As shown in the below image which is taken from PCI_Express_CEM_r3.0 Specification, How the Hot-plug control logic will detect the PCIe ...
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Lets say I have a signal that is X GHz, is there a specific anti pad size to ensure I have correct signal propagation? Does the anti pad only add a delay or extra capacitance?
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What are the things to be take care to avoid reflections when a PCB trace is routed in multiple layers. I mean, How to achieve impedance control when trace moves from one layer to other.
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I am trying to route several high speed JESD204B signals (up to 12GHz) to a connector and there is very small area for them. The manufacturer design note (p.113) recommends to route those signals on ...
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I'm currently debugging a high-speed amplifier circuit that seems to oscillate every time I connect an oscilloscope probe to it. Below is a schematic: I started by populating the circuit up to the ...
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I know that at the time of crosstalk Capacitive as well as inductive currents generate voltage drops on the victim line over termination resistors. I have three questions. 1)Why inductive crosstalk ...
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