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Questions tagged [high-speed]

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High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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What exactly is the definition of a high speed signal? Would you consider a signal of 1 MHz a high frequency signal? Or does it depend on the rise and fall time (the edges are what create harmonics)? ...
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I’m trying to understand the reasoning behind termination requirements in different differential signaling interfaces. For example, USB uses differential signaling (D+ and D–), but the standard does ...
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Does anyone know best practices for routing these types of connectors? My problem is that this type of connector requires vias. Firstly, I can't place the vias far apart from the D+ and D- pins (they'...
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For LPDDR4 T Branch topology layout routing do I need to match the length of Level 1 branch also with A0 with other address group like A1 A2 etc should be also equally length match. Level 1 branch ...
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I am working on a high speed design. To reduce the cross talk between the signals I need to implement a 5W rule (which means that the spacing between the signal pairs must be a minimum of 5 times the ...
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I have encountered a tow road selecting the order of layers in a 4-L stackup. Please consider the pcb has rmii, 2 x usb 2 full speed, qspi, sd card, and a tft controller parallel interface. Several ...
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I wonder if it's OK to use serpentine routing between vias at under the BGA package. If you look at DDR0_DQ27, you can see that I using that area to perform length matching by use serpentine routing ...
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I have a CAN Bus with a PCB at the center of the system. I have a pair of 120 ohm differential traces on the board. They are .45mm height above the reference plane and .45mm trace gap. Is there ...
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I'm designing a custom SBC using the TI Sitara AM6254 SoC, which includes several high-speed interfaces like DDR4, RGMII, USB,HDMI,LVDS,CSI and PCIe. The official SK-AM62B-P1 development board from TI ...
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I'm working on a 10-layer PCB design with high-speed signals and need some advice on return path via placement. My setup: 10-layer stackup Using buried and blind vias for high-speed signals Signal ...
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I am designing a standard 240 pin DDR3 UDIMM PC ram stick for learning purposes. I did quite a lot of research on the DDR3 architecture and PCB layout, but there are still some questions that I can ...
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I am trying to integrate the Raspberry Pi CM5 into a camera recording project but am not sure about exactly how to route the HDMI (and other differential) signals. I have a basic understanding of the ...
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I am currently in progress designing SoC based on AMD Zynq7010 with two DDR3 memory (MT41K256M16TW-107IT:P). I am utilizing fly by routing. Upper memory is 2nd DDR3 memory and lower memory is 1st DDR3 ...
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This is a general inquiry regarding differential signaling in common high-speed interfaces. Specifically, I have observed that Ethernet PHYs and USB hub ICs often include features such as polarity ...
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I'm designing a PCB with a bunch of controlled-impedance differential pairs. I've determined that I must go to an 8-layer board. I'd like to use one of these Hartley-recommended stackups: (Image ...
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I'm looking for a compact sensor solution to measure relative angular position for a rotating system under the following constraints: High-speed rotation: The system (and the sensor itself - it is ...
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Grosso modo, the standard input stage of a sampling circuit has traditionally the following form: simulate this circuit – Schematic created using CircuitLab In high performance sampling ...
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I am senior EE student and working towards high speed PCB board design including DDR3, Gigabit Ethernet, MIPI and HDMI. I finally completed schematic and moving towards PCB design. As expected, I am ...
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I have two ICs which will be communicating 100Mbps serial data to each other over a single ended transmission line. The communication is half duplex, so they will take turns being the transmitter and ...
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The ECP5 sysIO datasheet mentions two programmable skew rates (FAST and SLOW) for LVTTL and LVCMOS outputs but the actual slew rate value is never given. Has anyone measured the output signal rise ...
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I'm working on a project where I need to control a large number of shift register outputs updated at 44.1kHz audio rate. I built a board in the past that worked well for controlling 64 outputs (8 ...
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I'm using a USB2514-B as a 4-port hub connected to a Raspberry PI CM4, and I can't figure out why the USB devices connected to it only work in full-speed mode. If I connect a USB device in high-speed ...
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My circuit includes the following components: • PIC16 with internal clock, frequency: 32 MHz • ST LED2000 LED driver (a buck converter) with a PWM dimming input • TI BQ24070RHL battery charger • ...
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For education purposes, I plan to build the following short-pulse generating circuit: (picture taken from https://www.radiolocman.com/shem/schematics.html?di=473681, as far as I can tell the original ...
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I am working on power integrity analysis of a motherboard in HSpice, i.e. analysing the power distribution network (PDN) of a motherboard PCB to locate the regions of biggest noise or DC voltage droop ...
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I am designing a PCB which includes a BGA connector and differential pairs. The differential signals are Displayport and Ethernet. Those tracks go connector to connector only. I choose 0.2mm drill ...
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This will be my first attempt to design PCB based on Xilinx Zynq device. The specific part number is XC7Z010-3CLG400E. My main objective is to learn how to design high speed peripherals including DDR3,...
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Many times you see datasheets showcasing high speed transciever interfaces being tested using PRBS data. Intuitively, I think the motivation is to test the medium using a signal of somewhat even ...
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An FCC unintentional radiators test is failing at 550MHz, after probing with a near field probe the source was located to these areas of the PCB (shown below in black circles). The RMII is running at ...
Voltage Spike's user avatar
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Background While debugging a system where one of the peripherals was only intermittently present on the bus, I turned my attention to PCIe risers as a culprit. After measuring a few of them I noticed ...
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The AD9545 Evaluation Board documentation states that the Reference Inputs (REF B/BB) are "configured for single-ended CMOS inputs" and drive the AD9545 via an "on board voltage divider&...
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I am using a D-coded M12 Ethernet connector in my device for a Fast Ethernet (100 Mbps) connection. Due to physical limitations, the connector can't be PCB-mounted, so I selected a panel-mount version ...
HV16's user avatar
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I am using the Kicad trace width calculator tool for finding the width required for a 50 ohm trace. The obtained value of trace width is 0.355mm. Assume this trace width is not enough for the ...
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I need to design a PCB for RF Application. The board contains jsut 4 sma connectors .They are Connected as shown below. The frequency of operation is 20Ghz. Trace impedance should be 50 Ohm.Current ...
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I saw some routing the other day in a design, I'm wondering what would be better for less crosstalk. Version 1 has better matching but the diff pairs are closer to each other. Version 2 has better ...
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I need to add a small (~1 V) voltage with DC and AC (but not exclusively AC) components from a signal generator to a high DC voltage, up to approx. 500 V. Conceptually, the answer could look like ...
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I'm building a very low-cost bidirectional SDI-3G to fiber converter. I am in the process of selecting a connector for the SDI part. The issue is that I can't really find one that won't explode the ...
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I'm looking to build a mostly-passthrough HDMI device, but I'm finding it very confusing to understand the maximum speed that a connector can allow for. I've noticed that DigiKey, for example, shows &...
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One of my colleagues claims that no matter what frequency the PCB board has, you cannot allow reflections inside the tracks. In this case, it's 1 Hz frequency that is going to turn a relay ON. The ...
euraad's user avatar
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I have done many designs below 2GHz but am now needing to go beyond that to 3GHz. The PCB's need to be able to support MIPI CSI and LPDDR5 signaling. Can I use run of the mill FR4 or do I need to '...
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When running at a fast signal, why does the MOSFET below not turn off, even when gate voltage is well below threshold (even negative)? Although the signal is fast (7 MHz, 140 ns period) it is < 1/...
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I stumbled across a recommendation in an 850MHz opamp datasheet that said the following: All ground and power planes under the input and output pins must be cleared of copper to prevent the formation ...
Polynomial's user avatar
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I was testing my display port diagram, all 4 lines. The first three look good, the 4th line looks like it has only one signal (not differential.) My question: Is the 4th line okey to be like this. (...
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I have a 12 GHz oscilloscope with a 40 GSa/s sampling rate from Keysight, and I have a National Instruments GPIB-USB-HS with it. Sampling for 30 seconds with no averaging of data, it only gives 20 ...
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Assume you have a four layer board. Signal GND Dielectric VDD Signal And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer. Question The ...
euraad's user avatar
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I want to use a reference design form Texas instrument as a reference for my layout for OPA838, I noticed this reference design is a 4-layer board (signal-GND-Power-signal): Reference: the image is a ...
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What do we encounter if the impedance changes along the way? For example, what kind of problem can we encounter when one of the two complementary PCB's is 90 ohm and the other is 100 ohm? For example, ...
esat's user avatar
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Most of these days, the Ethernet PHY/switch devices support Auto-MDIX and Autonegotiation. So, when a link partner is getting connected to a PHY or a Switch, which of these two phenomenons happens ...
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I have a PCB design with a SMB connector but can't find any information about how I should treat the pad to ensure 50R impedance. Should there be a keepout on the ground layer directly beneath this ...
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I am designing a fast pulse generator, inspired by Leo Bodnar's pulse generator, using the ADCMP572 ultra fast comparator. It looks like a pretty simple device, using a PIC microcontroller to drive ...
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