I am designing a standard 240 pin DDR3 UDIMM PC ram stick for learning purposes. I did quite a lot of research on the DDR3 architecture and PCB layout, but there are still some questions that I can not answer on my own.
How does a dual rank configuration actually work? I understand the concept of it, but how do the two (different rank) DRAM chips distinguish, which one should respond? Given that there is only one chip select and only one clock enable pin on the UDIMM connector, all the other pins, including the data lane (DQS,DM,DQ) and control (CAS,RAS,WE,address etc.) are shared between the different rank chips too. Even if the CPU can do some internal memory mapping, the DRAM chips are still exposed to the exact same electrical signals (DRAMs do not have configurable address A0-A2 pins like EEPROMs, so there is no defined address to those.) I hope am wrong somewhere in this paragraph, otherwise it will be even harder to perceive...
Second question is about routing style between the ranks. I know that on double-sided PCBs, it's preferred to have a via that connects the same pin on both (different rank) chips. But if you take it as a given, that you have two DRAM chips on the single side next to each other, what is the preferred routing style: fly by or T-branch? If the T branch is preferred, should I split the track right at the beginning of the UDIMM module, or should I split it right before the minimum inevitable track length that is required to match the trace skew for both chips? If a fly by topology is preferred, is there any maximum tolerable stub length with respect to the first daisy-chained chip?
It was pretty hard to form the questions clearly, so I attached some sketches for clarification. I thank you in advance for any information provided.
