Questions tagged [lattice]
Lattice Semiconductor is a company that produces analog and digital FPGAs, including the ORCA FPSC assets.
125 questions
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FPGA stops communicating when power cycled
I'm working with a Lattice FPGA (LCMXO2-1200HC-4TG144C) and a program that has always worked until now. This problem is driving us nuts.
Recently, I made a new PCB with a new FPGA and other components....
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Lattice ECP5 output slew rate not in datasheet
The ECP5 sysIO datasheet mentions two programmable skew rates (FAST and SLOW) for LVTTL and LVCMOS outputs but the actual slew rate value is never given.
Has anyone measured the output signal rise ...
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Simple PMOD connector situated upside down from what's documented on an Icestick FPGA evaluation board?
Referring to the Icestick evaluation kit for the iCE40-HX1K FPGA.
The board has a PMOD 12 pin connector. According to the board's manual, as well as various other online sources, the GND and 3.3V pins ...
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Can I Use a Buck Converter to Step Down USB Power to 3.3V and Increase Current?
I'm a newbie in electronics and working on a project where I want to power a custom FPGA board via USB-C 2.0. The USB source provides 500mA.
I’m planning to use a buck converter to step down the 5V to ...
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Small Resistors on Power Supplies of Lattice iCE Development Kits?
What is the function of R30 and R35 in the Lattice iCE development kits (iCE40HX-8K Breakout Board or iCEstick)? One possibility I've considered is that they help limit ramp rates or control the power-...
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FIFO Not Storing Sequential Data Correctly in ICE40UP5K FPGA – Possible Timing Issue
A bit relevant data about the project
I'm working on a project that includes sampling a 10 MHz analogue signal at around 60 Msps on an ADS4222 (2 12 bit channels). The clock is generated using the ...
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Lattice FPGA - RAM_DP - Write/Read Enable
In Lattice Diamond I'm using the “RAM_DP” EBR component from the IPExpress page.
The FPGA I am using is a LCMXO3LF-4300E-5MG121I.
I'm confused whether the “WE” input controls both writing/reading, or ...
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Lattice Diamond PLL Configuration for decimal output
I have been working on a Lattice FPGA to configure a 37.125MHz output for a 24MHz input clock... but the only way I have been able to accomplish getting this is with a 5% tolerance and a big ...
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Lattice FPGA - JTAG Programming 6Pin VS 10Pin
I'm using a Lattice MachXO3LF FPGA, specifically the LCMXO3LF-4300E-5MG121I, and I want program it using JTAG and the HW-USBN-2B programming cable from Lattice. In the Programming Cable Users Guide, ...
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MachXO2 VHDL Internal Oscillator - "ERROR: formal nom_freq is not declared"
I am trying to run the code below, but I get an error on line generic map(NOM_FREQ => "2.56"); and I am very confused why. The error says "ERROR - ...
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How does a Lattice MachXO3LF FPGA handle undefined IO states?
In the Lattice MachXO3LF FPGA, if an IO pin voltage is in between the thresholds for VIH min and HIL max, how does the FPGA handle this?
How does the FPGA handle if the undefined state was reached ...
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Lattice MachXO3 FPGA VIL and VIH of Mixed Voltage I/Os
The Lattice FPGA MachXO3 sysIO User Guide, page 12, under section "7. VCCIO Requirement for I/O Standards":
it mentions that an:
input buffer set up to be a 1.2 V ratioed input can be used ...
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Lattice MachXO3LF FPGA Internal Clock Accuracy
On the data sheet for the Lattice MachXO3 FPGA family, it shows that the internal oscillator has varying nominal frequencies with +/- 5% accuracy. Does this apply to its entire temperature range ...
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Reset issue while issuing commands to SD card
I am busy with a project where I'm trying to make a custom flashcard for the Gameboy (for more details, refer to https://efacdev.nl/projects/ecgc). For the flashcard, I am trying to load games from an ...
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Stateful logic synchronization clock with memory read/writes
I am working on a hobby project using Verilog and iCEstick evaluation board. I have a stateful logic (FSM) which needs to read and write to the on-chip block RAM. Now I am a little bit confused, it is ...
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Where to register value in Verilog?
I'm looking for some help understanding a synthesis error I run into frequently with Verilog code on an FPGA platform (Lattice ECP5U).
Here's a simplified setup that produces the error. ...
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Lattice Diamond timing errors in place and route with large registers
Is there a good way to generate a timer with at least 27bits of precision so the place and route doesn't fail? I've tried breaking up the timers into 4x8 bit timers, but it only makes the slack worse (...
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How can you find the maximum aggregate I/O current supply for a Lattice FPGA?
I want to find the maximum aggregate I/O current supply for the MachXO3D (9400HC) breakout board to ensure that I do not damage it. All pins will be using the LVCMOS33 I/O standard. I have been up and ...
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What do these symbols mean in Lattice Diamond software?
These two pin symbols are in the Lattice Diamond Device View, what is the difference between the two? They both say differential I/O pin when I hover over them.
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Are iCE5LP1K, iCE5LP2K and iCE5LP4K FPGAs actually the same device?
In official datasheet, iCE5LP1K has less logic elements than the larger models:
However, the iCEcube2 tool shows them all to consist of 20x24 array of logic blocks, each having 8 logic elements. This ...
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"Active Low" Button Circuit Never Records High
I have an FPGA Starter Kit (Lattice MachXO3) which I'm using 25 IOs for push buttons inputs. I'm driving the starter kit and button circuitry from the wall with a 12V AC/DC adapter (rated for up to 2A ...
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Use cases for "low pin-count" FPGAs
I recently came across the ICE40UL1K-SWG16ITR1K (Please see DigiKey, DE) 16-Pin FPGA.
This Device "packs an amazing punch" for its size:
57kBits of RAM
1248 Logic-Cells
156 LABs/CLBs
and is ...
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Tinyprog has issues programming the TinyFPGA-BX module on macOS M1
I have used TinyProg on Linux before to program the TinyFPGA-BX board just fine, but I am having issues with macOS on an M1 Powerbook. Apio finds the serial device just fine:
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FPGA patching existing program
This may be a beginner's question as I'm not that well versed in FPGA design.
What I basically have is a preprogrammed Lattice LFE5U-25F with an external memory and I don't have the source code of ...
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Is there a program to load a JED file and show as a schematic?
I have a JED file from a GAL 16V8 as an example.
Is there a tool to decode this into a schematic of gates and registers?
Coders: Is this a hard "interface" program to write to have ispLever ...
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IspLever5_1, Can I specify the I/O pins for Gal22V10 to meet a specific design?
File was generated from schematic input ABEL isplever5.1:
This is a "nothing-special" Shift register (Din/CLK), and tri-state output: EN.
Output pins are Labeled (KP_0 to KP_9) should be ...
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Is the place and route tool erroneously inferring a combinatorial loop from VHDL?
The problem is an inconsistency I observed when I compared the result of the synthesis step to the result of the P&R step. The P&R inserts a combinatorial loop which is not present in the ...
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FPGA Bank Voltage
If an FPGA bank is physically connected to a regulator voltage of 2.5V and in the software the bank is defined as 1.8V and the I/O standard used for the buffers is also 1.8V, the code compiles without ...
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Lattice MachXO3 - what's "HW Default Mode"?
What's the meaning of the "HW Default Mode" for a Lattice MachXO3 device? I've seen this term come up a few times in the configuration guide but there is no clear definition of it. Does this ...
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Configuring ICE40LP FPGA with STM32F4
I am new to STM32 programming and design, and my first project is to get an STM32F413 to program a Lattice ICE40LP FPGA (also a new platform...) via its slave SPI configuration interface (page 17). ...
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How to properly implement an n-FF synchronizer in Lattice FPGAs?
Unlike Xilinx which provides their users with a set of convenient xpm_cdc_* modules, Lattice does not seem to have “the standard” way for clock domain crossing. So ...
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Error: timed out while waiting for target halted
trying to debugging project OpenOCD on Lattice Crosslink-NX device, but I'm catch an error:
...
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How to change the pin type in Lattice Radiant
I'm using IP-core with slave-device clock in Lattice Radiant. On the Device Constraint Editor this pin determinated as clock-pin and I can't place it on correct pin on FMC.
This question is similar to ...
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How to increase setup time of a reg wired to an EBR FIFO? (Lattice FPGA)
I'm using the built-in EBR FIFO of a Lattice FPGA:
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Lattice ICE40-LP1K 84-QFN SPI Flash Programming
I'm using ICE40-16-WLCSP-Eval-Kit as a reference design for the Lattice ICE40-LP1K 84-QFN which I'm going to use in the motherboard I'm designing.
I did a little experiment with ICE40-16-WLCSP where I ...
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Internal Pull-Up (PU) for LATTICE ICE40 LP1k
I'm using AD8541 Amplifier as a Power Good indicator for +VCCST_CPU that comes from Intel Tiger Lake UP3 on the motherboard I'm building.
The outputs V5S_OK and VCCST_CPU_OK go to an ICE40 LP1k FPGA.
...
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Flash terminology and meaning
I am trying to choose an SPI flash device for my FPGA and I want to verify if I am understanding the terminology correctly.
Bitstream is the configuration data code used to implement the logic in the ...
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FPGA pin numbers
I'm having trouble understanding the structure of FPGA datasheets.
From what I can tell, there is usually a table of "Signals Descriptions" with the pin names and their function, but I don't ...
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FPGA pins driven high at power-up ‒ what can I do to get around this?
I have a board that uses a Lattice XP2-8 (BGA256, in case it makes any difference).
Some FPGA pins are connected directly to LEDs with positive logic. That is:
simulate this circuit – Schematic ...
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IO Type (LVCMOS25, LVCMOS18, etc.) in FPGA pins
In Lattice Diamond, spreadsheet view where I assign the signals to pins of the FPGA chip, there is IO type. Restricting the discussion to single-ended CMOS signals, then my choices are given by the ...
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Why is this power-on reset generator Verilog module getting optimized out?
I am trying to write a Verilog module that generates a power-on reset signal for a few clock cycles. I am synthesizing using Lattice iCEcube2 + Synplify Pro targeting an iCE40 HX1K on the Nandland Go ...
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ECP5 Versa Board Example
I'm struggling to get my design on the ECP5 Versa board running. Currently it's just for hardware verification so there's not much going on. So this is my top entity...
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Lattice Diamond Clock Assignment issue with ECP5 Versa
I try to get a Lattice ECP5 Versa Board running but I struggle with the port assignment for my clock as I don't understand what exactly Lattice Diamond is doing. It's the first time I'm working with ...
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Lattice Diamond — How to identify which parts of design take most of FPGA resources?
I have a Lattice FPGA-targeted design which already takes approximately 95% of the SLICEs available on the device; pretty close to the chip capacity. Unfortunately, I need to add some more logic to it,...
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Lattice iCECube2 cannot find clock in .sdc file
I've tried a zillion different ways to get the lattice iCECube2 tools to find a generated clock.
How do I specify the .sdc file to see the output of baudgeninst, ...
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Which software tools from LatticeSemiconductor do I need to develop design with iCE40 LP FPGA?
There are a lot of programs that can be found here:
https://www.latticesemi.com/en/Products/DesignSoftwareAndIP
Which of these do I need for creating a design with iCE40 LP FPGA?
The reason for my ...
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Troubleshooting tinyprog when programming TinyFPGA BX: [Errno 19] No such device
I am using the TinyFPGA BX for the first time, and tinyprog crashes when I try to program the board.
First, I run apio build, ...
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No port matched and or doesnt connect to anything
Good evening,
I'm having some issues with some verilog code, or quiet a lot to be honest. Or with Lattice's software actually.. This was tried in Lattice Radiant.
First off, I'm getting these warnings(...
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Can propagation delays be simulated in Active-HDL?
I'm using the Lattice Diamond licensed version of Aldec Active-HDL. The logic circuits I'm working with are complex enough that I believe propagation delays could have an impact on the actual function ...
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Lattice FPGA: Mach X02 7000 Can it be used for DSP?
I have a MachX02 7000 having 6800 LUT's.
I want to implement DSP algorithm involving floating-point DSP algorithm on 2 14 bit ADC input data.
Is it possible to perform on this FPGA with low LUT's, No ...
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