Questions tagged [timing]
This tag is relevant to issues with timing of a protocol or a standard. This could contain UART/ IIC etc. timing as well as timing for driving a motor.
378 questions
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Understanding Tready Timing with EEPROM Connected to PHY (Max Tready 120ms)
I’m working with a PHY device as described in the datasheet (p. 158) of this PHY, and I’m trying to understand the Tready timing with an EEPROM connected to the device.
According to the datasheet, the ...
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Sample and hold (S&H) lower sample timing problem
I want to build a 1-octave keyboard and want to hold last note pressed. I hardly found some circuits online and they are working properly(ish) but when I press higher notes first and lower notes after,...
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Why does the 2‑wire asynchronous handshake use this exact edge sequence?
1. Control Models
Master / Slave
The master controls the communication line (decides when to transmit or receive).
The slave transmits or receives under the master’s command.
Peer‑to‑Peer (symmetric)
...
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Car central lock control pulse circuit
I had a central lock control circuit malfunctioning in my car. I tried to reverse engineer it and here is the schematic I came up with:
Figure 1. Schematic.
The driver's door lock has some kind of ...
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How are the PSTransitionTimer/tPSTransition for USB PD interpreted?
The USB Power Delivery specification has the following to say about the timer in question:
6.6.5.1
PSTransitionTimer
The PSTransitionTimer is used by the Policy Engine to timeout on a PS_RDY Message. ...
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Power Supply timing specification
Using this E51 microcontroller in a project.
On page 1853 of the datasheet, the rise rate specifications for the microcontroller's power domain are provided. I am supplying the device with a fixed 3....
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525
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How to generate 640x600 resolution on a VGA monitor?
If a monitor can display 640x480 and 800x600 resolutions, then is it possible to display 640x600?
I am generating my own video signals with an FPGA and an LCD monitor (1680x1050 max resolution, but ...
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How can I design a circuit using only discrete components (no ICs and no logic gates) to control four bulbs in this sequence? [closed]
Bulb 1: ON for 16s, then OFF → Bulb 2 turns ON.
Bulb 2: ON for 8s, then OFF → Bulb 3 turns ON.
Bulb 3: ON for 12s, then OFF.
Bulb 4: Turns ON 12s after Bulb 1 and stays ON for 12s.
The cycle repeats ...
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103
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Mistake in Proper Timing Constraining QSPI Flash
I have a Zynq-7020-based FPGA board and a QSPI Flash IC (Micron Serial NOR Flash Memory, part number: MT25QL128ABA). I want to interface with this flash in quad mode (i.e., using all four lanes for ...
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How to specify clock period in Synopsys Design Constraints file (SDC)?
The SDC file:
create_clock –period 37 –waveform {0 18.519} {clk}
While reading SDC file in the Quartus, I get following error:
...
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SSD1306 I2C `ack` bits on Open Drain Implementation
I am trying to get an ack message response on my SSD1306.
To send the signal, I am using a 27MHz FPGA clock, divided so that the clock cycle is around ...
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SSD1306 OLED IIC timings ACK
I am looking to make sure my understanding of the ack signal is correct for the SSD1306
Based on some previous questions, I have changed the signal I am sending out ...
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SSD1306 initialisation timings I2C
I am trying to make sure I have understood the I2C timings correctly for the SSD1306.
As an example, I have shared below the ...
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495
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Capacitor delay circuit specific component selection
I’m looking for advice on how to design a time-delay relay circuit using discrete components (rather than, say, a CMOS or 555 chip). The goal is to have delay between the switch being closed and the ...
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Need delay circuit to pull IC pin low for 10 seconds [closed]
For a RF project I use HT12D decoder. I have sensor with digital output. Whenever sensor value changes from low to high or high to low HT12Ds TE pin must be pulled low to enable transmission for 5-10 ...
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FIFO Not Storing Sequential Data Correctly in ICE40UP5K FPGA – Possible Timing Issue
A bit relevant data about the project
I'm working on a project that includes sampling a 10 MHz analogue signal at around 60 Msps on an ADS4222 (2 12 bit channels). The clock is generated using the ...
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Help to solve 74LS85 comparator
I am working on a 4-bit comparator problem using a 74LS85 chip. I have two 4-bit binary inputs, A and B, and I am trying to determine the output signals (A = B, A > B, A < B) based on the timing ...
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What to watch out for in combinatorial logic in reset value?
I have a register that I want to update using two different mechanisms
Shifting left, triggered by signal a
Updating the whole value, triggered by signal ...
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AT25SF081 SPI Flash waveform timing verification
I am again looking at Figure 11-1 Read Manufacturer and Device ID Signal for the Flash device in the title.
I have created this diagram to describe my plan for implementing this operation:
As can be ...
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AT25SF081 SPI Flash SO start and end timing
I am now looking into the Figure 11-1 Read Manufacturer and Device ID Signal.
Say my code correctly clocks in the relevant OPCODE on SI.
However, maybe then the software waits a little too long (or ...
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AT25SF081 SPI Flash Waveform relative to FPGA testbench
I am now looking to understand more on the IO waveforms on the AT25SF081 Flash memory documentation in relation to the controlling device.
Are the waveforms in the document from the 'point of view' of ...
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AT25SF081 SPI Flash to 12MHz FPGA signal timing
I am trying to understand how the timing of signals work between a 12 MHz FPGA, and a connected AT25SF081 SPI Flash device.
In my specific situation, I am trying to perform a status register read. It ...
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AT25SF081 SPI Flash device terminology
I have a third question on the AT25SF081 Flash Datasheet Table 1-1.
In the Table 1-1 there are the statements: ...
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How do I calculate the frequency of this 555 Toy Organ circuit (from Mim's Radio Shack book)?
So, I've got the circuit below (from Forest Mim's 555 Radio Shack book), and I want to try to verify the first frequency ( 52 Hz @ .22 uF). I basically don't know what I'm doing, so I'm going to take ...
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RC timing circuit
I'm reading AOE 3rd edition, book say below:
Here’s how the circuit works: the voltage divider R3R4
holds the (−) input at 37% of the supply voltage, in this
case about +1.8 V; let’s call that the “...
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212
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SDF Annotation of gate-level sim. Defining scope for $sdf_annotate
I have a gate netlist for an 8 bit adder.
...
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4
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894
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How can I make a PAL sync generator without a microcontroller?
I would like to build a SIMPLE circuit that generates PAL sync signals with no MCUs, because they don't make any ICs of these kind anymore. I have already tried a solution, but I think it is ...
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108
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What determines I2C interrupt service time after address byte ACK?
I am looking at the NXP spec for I2C and what I don't understand is the timing constraint for the portion of the transmission where the "clock line held LOW while interrupts are serviced" (...
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442
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Wiring the output of a D flip-flop to its input
I've got a simple question about flip-flops, particularly the SN74LS175.
I want to know if it's possible to wire the output of the flip-flop through some combinatorial circuit and then back into the ...
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How to improve mosfet switching timing?
I am a hobbyist and I am not a native so bear with me please. I was looking for a fast mosfet and by looking at some datasheets I noticed that switching time is not a constant parameter like this one:
...
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What specs should i look for for a mosfet in this project? [closed]
I am a hobbyist and not a native so bear with me. I need a MOSFET that can switch at ~ 100 MHz and withstand up to ~ 40 V and 40 A with a variable duty cycle. If my calculation corrects 1/100 MHz ...
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FPGA DDR timing constraints
I have EMMC master for FPGA. Please tell me how to write constraints on ports in DDR mode? I tried to write constraints but I doubt the correctness
Specification:
JEDEC Standard No. 84-B51
P.S. Here ...
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Optimizing Incandescent Traffic Light Design
I'm currently working on designing an incandescent traffic light system and could use some guidance on extending and optimizing my design. Initially, I've successfully implemented the required ...
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STM32 writing to SD card using FATFS sometimes takes longer than normally
I am using nucleo-f401re board for my project and I want to write sensor data to SD card. I am writing data when sensor interrupts occur, and that happens at 408 Hz, so I have around 2 ms to write ...
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Would this boot select button design work?
So, I'm back with the need for more advice. This post ties in with my previous post
here. I recommend you read the previous post because most of the information that I'll be referring to is found ...
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How to interpret maximum risetime on I²C communication timing specification
I am using a ICM-42605 IMU in conjunction with a GNSS module, which has a blackbox firmware that realizes the communication with the IMU via I²C. I can see signs that the communication works fine, and ...
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Are same row pixels exposed simultaneously for rolling shutter sensor in ERS mode?
I know that each pixel row in a rolling shutter sensor running in ERS mode (Electronic Rolling Shutter) are exposed for the same duration but at different points in time. But what about each pixel in ...
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456
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Driving Gate from MCU (using 6N136 and TC4431)
This is my first time trying to use this optocoupler (6N136)
I'm trying to control a MOSFET gate with the least switching delays (rise and fall timings) possible, while making the MCU isolated from ...
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FPGA output timing explained
As a hardware designer you have consider the timing constraints of both the input and output device. Input devices specify a setup and hold time reference to the clock (the time in which the data ...
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Horizontal Blanking Interval (Idling Time) optimization
I have questions regarding the time slot in-between two frames of video stream, i.e. Horizontal Blanking Interval (let's say HBI in the following), seen as Idling Time sometimes.
Considering a CMOS ...
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Z80 interfacing, address decoding logic produces noisy signals
I really would like to have suggestions and feedback from someone. It's about digital logic, in detail, the Z80 interfacing.
In this design, I used a 74HC30 which is a 8-input NAND Gate.
I'm using it ...
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Timing parameters of sequential circuit - digital electronic
Problem
Determine the timing parameters (\$T_\text{cQ,bb}, T_\text{su,bb}, T_\text{h,bb}\$) for the black box logic circuit seen below: -
Attempt
\$T_\text{cQ,bb}\$ is the time it takes for the ...
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Synchronization of handshake channel with different clock domains
My course on design of digital systems uses the book "Introduction to Asynchronous Circuit Design" by Jens Sparsø.
On page 156 he talks about synchronizing a handshake protocol between a ...
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A 555 timer changes time when you touch it?
I designed a simple 555 astable 50% duty cycle square wave generator, assembled in China on SMT PCB. It works well: Except when you touch it, or even put your fingers near it, the timing changes ...
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Erratic and confusing I2C behavior between ATSAMD21G18 and A89307 through ISO1644 isolator
I'm working on a BLDC driver using Allegro's A89307 controlled by an isolated ATSAMD21G18 via TI's ISO1644 I2C digital isolator. The simplified I2C connection is shown below, I omitted all the bypass ...
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ADC Timing Problems in FPGA design
I am using a Xilinx Kintex UltraScale FPGA (AXKU040 development board) and an ADC board (FL9616 board). I would like to have a design that provides the ADC data as a data stream inside the FPGA. The ...
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458
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How to write I2C protocol timing constraints?
How do you normally write clock timing cons for I2C? Assuming 1 SDA line, 1 SCL line, 1 APB reference CLK called PCLK.
Q. What are the relation of PCLK to SCL in this protocol? Does it matter if it is ...
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Best practice to constrain dynamically tuned FPGA->DAC data path
Data is moved from the Zynq 7010 to AD9779A DAC using parallel SDR link at 155.52MHz. This DAC generates DATACLK clock that is used to clock data out of the FPGA (see picture for the relevant FPGA ...
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Why does increasing the period of a signal compensate for clock skew?
My textbook gives the following circuit:
simulate this circuit – Schematic created using CircuitLab
Where both registers are positive-edge triggered D-Type flip-flops.
It describes a how a race ...
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