I have a gate netlist for an 8 bit adder.
module my_add ( clk , rst , a , b , sum ) ;
input clk ;
input rst ;
input [7:0] a ;
input [7:0] b ;
output [7:0] sum ;
FF1Q_X10_R \temp_sum_reg[5] ( .D ( N2 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[5] ) ) ;
FF1Q_X10_R \temp_sum_reg[4] ( .D ( N3 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[4] ) ) ;
FF1Q_X10_R \temp_sum_reg[3] ( .D ( N4 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[3] ) ) ;
FF1Q_X10_R \temp_sum_reg[2] ( .D ( N5 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[2] ) ) ;
FF1Q_X10_R \temp_sum_reg[1] ( .D ( N6 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[1] ) ) ;
FF1Q_X10_R \temp_sum_reg[0] ( .D ( N7 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[0] ) ) ;
HA1_X5_R \add_15/U_0 ( .A0 ( a[0] ) , .B0 ( b[0] ) ,
.CO ( \add_15/N_17 ) , .S0 ( N7 ) ) ;
FF1Q_X10_R \temp_sum_reg[6] ( .D ( N1 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[6] ) ) ;
FF1Q_X10_R \temp_sum_reg[7] ( .D ( N0 ) , .TI ( 1'b0 ) ,
.TE ( 1'b0 ) , .CP ( clk ) , .R ( rst ) , .Q ( sum[7] ) ) ;
FA1_X5_R \add_15/U_3 ( .A0 ( a[1] ) , .B0 ( b[1] ) ,
.CI ( \add_15/N_17 ) , .CO ( \add_15/N_21 ) , .S0 ( N6 ) ) ;
XOR3_X10_R \add_15/ctmi_12 ( .A ( a[7] ) , .B ( \add_15/N_38 ) ,
.C ( b[7] ) , .Z ( N0 ) ) ;
FA1_X5_R \add_15/U_5 ( .A0 ( a[2] ) , .B0 ( b[2] ) ,
.CI ( \add_15/N_21 ) , .CO ( \add_15/N_24 ) , .S0 ( N5 ) ) ;
FA1_X5_R \add_15/U_8 ( .A0 ( a[3] ) , .B0 ( b[3] ) ,
.CI ( \add_15/N_24 ) , .CO ( \add_15/N_28 ) , .S0 ( N4 ) ) ;
FA1_X5_R \add_15/U_10 ( .A0 ( a[4] ) , .B0 ( b[4] ) ,
.CI ( \add_15/N_28 ) , .CO ( \add_15/N_31 ) , .S0 ( N3 ) ) ;
FA1_X10_R \add_15/U_13 ( .A0 ( a[5] ) , .B0 ( b[5] ) ,
.CI ( \add_15/N_31 ) , .CO ( \add_15/N_35 ) , .S0 ( N2 ) ) ;
FA1_X5_R \add_15/U_15 ( .A0 ( a[6] ) , .B0 ( b[6] ) ,
.CI ( \add_15/N_35 ) , .CO ( \add_15/N_38 ) , .S0 ( N1 ) ) ;
endmodule
I also have an SDF file with cell delays, for example
(CELL
(CELLTYPE "FA1_X5_R")
(INSTANCE add_15/U_15 )
(DELAY
(ABSOLUTE
(COND !B0 && CI (IOPATH A0 CO (0.12::0.12)(0.13::0.13)))
(COND B0 && !CI (IOPATH A0 CO (0.13::0.13)(0.14::0.14)))
(COND !A0 && CI (IOPATH B0 CO (0.11::0.11)(0.11::0.11)))
(COND A0 && !CI (IOPATH B0 CO (0.11::0.11)(0.12::0.12)))
(COND !A0 && B0 (IOPATH CI CO (0.10::0.10)(0.11::0.11)))
(COND A0 && !B0 (IOPATH CI CO (0.09::0.09)(0.11::0.11)))
(COND !B0 && !CI (IOPATH A0 S0 (0.10::0.10)(0.13::0.13)))
(COND !B0 && CI (IOPATH A0 S0 (0.18::0.18)(0.16::0.16)))
(COND B0 && !CI (IOPATH A0 S0 (0.19::0.19)(0.17::0.17)))
(COND B0 && CI (IOPATH A0 S0 (0.12::0.12)(0.10::0.10)))
(COND !A0 && !CI (IOPATH B0 S0 (0.10::0.10)(0.13::0.13)))
(COND !A0 && CI (IOPATH B0 S0 (0.16::0.16)(0.15::0.15)))
(COND A0 && !CI (IOPATH B0 S0 (0.17::0.17)(0.15::0.15)))
(COND A0 && CI (IOPATH B0 S0 (0.11::0.11)(0.10::0.10)))
(COND !A0 && !B0 (IOPATH CI S0 (0.08::0.08)(0.12::0.12)))
(COND !A0 && B0 (IOPATH CI S0 (0.16::0.16)(0.13::0.14)))
(COND A0 && !B0 (IOPATH CI S0 (0.15::0.16)(0.14::0.14)))
(COND A0 && B0 (IOPATH CI S0 (0.11::0.11)(0.09::0.09)))
)
)
)
I would like to do a back-annotated gate level simulation, so I added the following instruction to my testbench.
// Stimulus process
initial begin
$sdf_annotate("../rtl_synth/gate_netlist.sdf", uut, ,"simu.log");
...
However when I elaborate my simulation I get two warnings and the following SDF statistics.
xmelab: *W,SDFINF: Instance add_15 not found at scope level <top-level> <../rtl_synth/gate_netlist.sdf, line 305>.
xmelab: *W,SDFINF: Instance add_15 not found at scope level <top-level> <../rtl_synth/gate_netlist.sdf, line 367>.
Annotation completed with 0 Errors and 2 Warnings
SDF statistics:
No. of Pathdelays = 185 No. of Disabled Pathdelays = 0 Annotated = 4.32% (8/185)
No. of Tchecks = 96 No. of Disabled Tchecks = 0 Annotated = 0.00% (0/96)
I would like to understand how setting my uut as the scope gives such poor annotation coverage.
