Questions tagged [asynchronous]
The asynchronous tag has no summary.
26 questions
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Full flag in asynchronous FIFO?
My question is about calculation of full flag for an asynchronous fifo:
rdptr is grey code of read pointer which is synchronized to write clock.
Original read pointer increments on read operation and ...
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2
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133
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Why does the 2‑wire asynchronous handshake use this exact edge sequence?
1. Control Models
Master / Slave
The master controls the communication line (decides when to transmit or receive).
The slave transmits or receives under the master’s command.
Peer‑to‑Peer (symmetric)
...
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Why does my synchronous mod-19 counter goes to (2,2) -> (2,3) -> (0,2) while the asynchronous version resets cleanly?
I'm designing a mod-19 counter in Logisim using two 3-bit (mod-8) counters:
Counter A – low-order bits (0…7)
Counter B – high-order bits (0…2)
1 Asynchronous version (works)
Clock drives A directly.
...
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Vivado Simulation Bug for 4 bit asynchronous ripple counter
I am currently learning Verilog and tried to build an asynchronous counter using T flip flops.
But, during the simulation, my most significant three bits become one without any clock signal from the ...
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1
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why does Quartus Prime shows a path as failing in case of CDC even though synchronizers are used?
suppose a signal is coming from a slower to a faster clock domain, and 2 levels of synchronizing FFs have been used, then the tool shows failing path from the launch node to the first synchronizing ...
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141
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2DFF synchronizer output was determined to be a clock by timing analyzer
I'm the newbie in FPGA.
I want to design a frequency counter, so the design will involved some CDC problem.
Therefore, I used FIFO (I use the Quartus FIFO IP) and 2DFF synchronizer in my design.
Below ...
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4
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549
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What is the best way to use asynchronous ("non-blocking") delay in embedded systems?
Background
I understand, maybe I'm wrong, an asynchronous delay would be one that does not completely take over the CPU.
On the other hand, the synchronous delay remains in a loop, counting clock ...
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441
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3 bit Asynchronous Counter
> Blockquote
In our lab, using digital trainer kit, we designed the 3 bit asynchronous counter using JK flip flops by connecting clock to pin 1, following this circuit:
We had three inputs that ...
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1
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Self clock synchronization in NRZ-I encoding
I was going through NRZ-I encoding technique, somebody mentioned that long stream of 0's will cause loss of synchronization in NRZ-I encoding scheme. But how?
What I understand is the receiver should ...
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How to interpret timing of cascading async SRAMs
I am reading the datasheet for a 32k × 8 asynchronous SRAM (part IS61LV256AL) and wondering how to apply the timing diagram to the following circuit:
We have three identical SRAM parts with inputs ...
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?
I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
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Can a buck converter functioning in CCM have non-linear behaviour at light load currents?
I've been designing a Simulink/Simscape model of a TI buck converter launchpad (https://www.ti.com/tool/BOOSTXL-BUCKCONV) and I'm trying to have my model fit the behavior of the device.
The board can ...
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740
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D Flip Flop Design on Logisim
I am trying to build a D flip-flop but I can´t get rid of those red wires. Is there a way to solve this?
EDIT: I was able to fix it manually through step-by-step simulation, but I still would like to ...
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2
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264
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Interfacing TLC59731 with Attiny85
Has anyone had any experience communicating with a TLC59731 from an Attiny85? I'm not sure how to configure the USI to support the EasySet "protocol" described in the datasheet. I imagine I ...
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Verification of asynchronous FIFO
I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.
The goal is to verify this design by using the Tb components, so no UVM at all. I ...
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1
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147
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Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?
For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
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1
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73
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Can I use a 3-phase driver like FNB41560 on 1- and 2-phase motors too?
I want to reduce complexity on buying many different parts and design different circuits. So I'm thinking if I can buy just FNB41560s that are well priced and simple and are capable of driving 3-phase ...
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1k
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Timing Async Reset with Sync Deassert
I've been reading about FPGA resets, particularly the links in benefits of removing reset in an FPGA design and the article http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf. For my ...
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STA timing closure for asynchronous FIFO
I have implemented an asynchronous FIFO
However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.
Both read_clk and ...
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4
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1k
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How are "async/sync" and "serial/parallel" communications related?
I think "async/sync" and "serial/parallel" are orthogonal concepts. There can be 4 combinations of communication types:
async serial
sync serial
async parallel
sync parallel
From ...
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Does this combinational lock circuit contain any memory?
Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
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Initializing feedback signal in ModelSim simulation
I'm trying to simulate a MOUSETRAP asynchronous pipeline for FPGA. For the control stage, I need to implement the following circuit:
DELAY is a delay element which I have correctly implemented using ...
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3
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Why does a 4-bit asynchronous counter need exactly 4 flip-flops?
We can get the same result (counting from 0000 to 1111) by removing the last flip-flop (Q3 output) and taking clock line as one of the inputs (i.e Q0 will be from clk itself and rest 3 outputs from 3 ...
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466
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Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?
I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from ...
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Why is asynchronous data transfer only suitable for slow devices?
I have read that asynchronous data transfer is wasteful of CPU time for slow devices like keyboard or mouse.
Then how is it possible that it is suitable only for slow devices like keyboard or mouse ...
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