I am reading the datasheet for a 32k × 8 asynchronous SRAM (part IS61LV256AL) and wondering how to apply the timing diagram to the following circuit:
We have three identical SRAM parts with inputs coming from the top and outputs going to the bottom and with the latter two having one of the bits driven by the output of the previous part. The timing diagram indicates that the output will settle by tAA (10ns for this part).
So what does this mean for cascading parts? The output of the previous part will move around a bit before it settles. Presumably if that settling includes changing the value of the one of those bits that's being used as input for the next part it will take 10ns for the first part to settle, which means to be safe we have to wait until those 10ns are up before we can assuming that the second part can start the proverbial 10ns timer, correct? So on the safe side we will need to wait 30ns for everything to settle in the entire circuit, correct?
But what really is going to happen with the circuit? How much effect is that one bit moving around before it settles going to affect the settling of the next part?
Does tOHA extend the time at all?
Does it matter if that one bit is the LSB or MSB?
