I'm the newbie in FPGA.
I want to design a frequency counter, so the design will involved some CDC problem.
Therefore, I used FIFO (I use the Quartus FIFO IP) and 2DFF synchronizer in my design.
Below is my RTL picture:
More information for the 2DFF synchronizer :
OK, here comes the problem.
When I use Timing Analyzer to deal with the timing constraints,
the system always gives me a warning like this:
Warning (332060): Node: synchronizer:S1|DFF_SYNC:D2|Q was determined to be a clock but was found without an associated clock assignment.
Info (13166): Register FIFO_2:FIFO2|dcfifo:dcfifo_component|dcfifo_m9q1:auto_generated|altsyncram_b1b1:fifo_ram|ram_block11a10~porta_datain_reg3 is being clocked by synchronizer:S1|DFF_SYNC:D2|Q
The Node: synchronizer:S1|DFF_SYNC:D2|Q I think it shouldn't be a clock signal,
It's just a signal that I want to synchronize to the clk domain.
I used to have a previous sdc file, and in the previous sdc file, this problem didn't exist,
but after I restart a new sdc file, and do the same constraints (maybe, I don't really sure about this ) as the previous one, this warning shows up.
Can somebody tell me what's wrong with it? And how to fix it?
