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How to decrease system clock frequency in Quartus II from standard 50 MHz to 2 Hz (two clock fronts per second)?

I find out it easier using constraints editing way, namely, SDC (Synopsys Design Constraints) file editing. But, don't know how do it exactly.

I work in Quartus II 9.0 (Build 132 02/25/2009 SJ Web Edition) and use the device Cyclone III (EP3C16F484C6) is placed on the Altera DE0 Board.

Was tried changing of the TimeQuest settings: was uploaded SDC file containing the line: "create_clock -period 500 [get_ports my_clk]"

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Timing constraints don't change the functionality of the design. They simply tell Quartus what your design does.

If you feed in a 50MHz clock, it will run at 50MHz regardless of what frequency you tell Quartus it is running at. The only difference telling Quartus a different frequency will make is all the timing reports will be wrong.

If you want to make 2Hz, you will have to implement a clock divider circuit. That sounds very much like a homework exercise, so I will leave it as an exercise to the reader. We see many questions asking this, so best advice would be to do some research for similar questions.

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  • \$\begingroup\$ Yes, I know what is frequency divider, but is possible to use built in capapabilities of FPGA, namely its PLL (Phase-Locked Loop block), to divide this frequency? Whether FPGA doesn't have own divider circuits? If does have, how to create constraints, namely SDC file, which have an affect on configuration file while creating it in such way that the devider circuits will be used? \$\endgroup\$ Commented Oct 13, 2024 at 11:19
  • \$\begingroup\$ Using of built in capabilities of FPGA could decrease count of used FPGA resources after programming it. \$\endgroup\$ Commented Oct 13, 2024 at 11:23
  • \$\begingroup\$ @VladislavButko The PLLs if any won't go down to 2Hz. You need a clock divider circuit. The FPGA doesn't have a "built in" clock divider - it's a highly configurable device that you can simply implement it in logic. Refer to the Cyclone III Device Handbook, it will tell you everything the device is capable of. \$\endgroup\$ Commented Oct 13, 2024 at 11:27
  • \$\begingroup\$ As stated, SDC constraints do not impact the design. They are to tell the timing analyser what you have implemented. So even if there were a built in clock divider (which there isn't), a timing constraint (SDC file) couldn't impact whether or not it would have been used. \$\endgroup\$ Commented Oct 13, 2024 at 11:31

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