module teset(
input clk,
input rst ,
input acc_end,
input weight_cnt,
output [4:0] acc_end_cnt_0
);
reg [4:0] acc_end_cnt;
always @(posedge clk or negedge rst) begin
if (rst == 1'b0)
acc_end_cnt <= 0;
else if (acc_end || (weight_cnt == 0 && acc_end_cnt != 0))
acc_end_cnt <= (acc_end_cnt >= 16) ? 0 : acc_end_cnt + 1;
end
assign acc_end_cnt_0 = acc_end_cnt;
endmodule
This is the code, The function is to update the acc_end_cnt ,when I synthesize in Vivado，the total hold slack is negative，
here are the time.xdc
create_clock -period 5 -name clk [get_ports clk]
Here are the design timing summary
It's strange why the total hold slack is negative when synthesizing, but it becomes positive after implementation
