Lattice FPGA - RAM_DP - Write/Read Enable

Question

In Lattice Diamond I'm using the “RAM_DP” EBR component from the IPExpress page. The FPGA I am using is a LCMXO3LF-4300E-5MG121I.

I'm confused whether the “WE” input controls both writing/reading, or only writing. There's separate inputs for write/read addresses and clocks and clock enables.

Assuming RdClock was always running, and RdClockEn was always enabled, and RdAddress had a valid address, would this always be reading regardless if WE was enabled or not?

I feel some of these input controls would be redundant if you could only read or write at a time.

Here is a link to “Memory Usage Guide for MachxO3L Devices.” I had trouble finding information that answered my question.

Dave Tweed · Accepted Answer · 2024-07-31 20:59:04Z

"Dual Port" means that there are two entirely separate ports for accessing the RAM array. In this case, one of the ports is strictly for writing and the other is strictly for reading. (Other types of FPGAs have read/write capability on both ports.)

So, WE is associated with the write port, and is strictly for writing. It does not affect the read port at all.¹ The other signals associated with the write port are WrAddress, Data, WrClock and WrClockEn.

The signals associated with the read port are RdAddress, RdClock, RdClockEn and Q.

Note that each port has its own clock, and therefore its own clock domain. The Reset signal appears to be global, and is probably treated as an asynchronous input in both domains.

¹ Unless you happen to be writing the same address that you're reading. In that case, the timing of the data update at the Q output might be a bit funky.

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