Questions tagged [xilinx]
A popular manufacturer of FPGAs (Field Programmable Gate Arrays) and CPLDs (Complex Programmable Logic Devices).
745 questions
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Using LUT RAM for an array of structs in Vivado
I'm trying to synthesize the following hardware in Vivado, which contains an array of my_struct_t. To reach timing closure, it's important that this array is ...
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What's the difference between 'EXTRACT_ENABLE' and 'DIRECT_ENABLE'?
Both attributes are used to tell Vivado if we want to use the enable pin of a DFF. What's the difference between them? When is one more preferable than the other?
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What does 'clocked out' mean?
In 7 Series FPGAs Configuration (UG470), Xilinx says,
DOUT is the data output for a serial configuration daisy-chain. DOUT is clocked out on the falling edge of CCLK.
What does it mean by 'clocked ...
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63
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Unable to control IIC sensor using JTAG to AXI Master and AXI IIC Xilinx IPCore
I'm trying to communicate with a temperature sensor (TMP461) without using the PS, relying solely on the Programmable Logic. For this purpose, I'm using JTAG to AXI bridge and the AXI IIC IP provided ...
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Can I program ZCU106 (Zynq Ultrascale+ MPSoC) with Simulink Embedded Coder without Vitis?
I’m new to working with the ZCU106 (Zynq Ultrascale+ MPSoC) evaluation board and am trying to write a simple "Hello World" program (e.g., toggling a user LED) using Simulink Embedded Coder ...
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57
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Risetime of DDR3 clock signal AMD Xilinx
I am using ZYNQ7010 SoC from Xilinx (AMD) to control two DDR3 memories with fly by routing. I am trying to run simulation to check signal integrity overall. Where can I find risetime information for ...
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68
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JTAG Not Working On TE0720/TE0706/TE0790-03
I am a uni student familiar with xilinx products and I have never used trenz electronics but I can't seem to establish a connection through jtag using the trenz electronics te0720 with the te0706 ...
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Spartan-6 MIG DDR3 Write Issue: Incorrect DQS to CK Alignment
I'm implementing a DDR3 controller using Xilinx MIG on a Spartan-6 XC6SLX16-2FTG256 FPGA. The DDR3 memory I'm using is MT41J128M16. The issue is that, during write operations, the upper byte (DQ[15:8])...
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270
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Zynq SoC Schematic review
I am kind of finishing up hardware design based on AMD Zynq 7010 SoC which has different peripherals. This is the most complex design that I have done in my past and I wanted to get some sort of ...
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159
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Programming Xilinx board using FT232 breakout board
Im trying to program my board via the FT232 because I'll be using that chip in my own development board around the same SOM my dev board uses (MYD-C7Z020 V2). My board doesn't show up in HW manager. ...
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MIPI D-PHY Image sensor with SoC
I am using this image sensor and interfacing with FPGA (Zynq 7010). I understand what needs to be terminated on FPGA side and I understand what I/O is supported such as LVCMOS18_F_8_HP, ...
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133
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AMD Zynq SoC with HDMI
I am relatively new to FPGA board design.
I am interfacing HDMI TX to FPGA (Zynq 7010 SoC) as shown below. My understanding is that Zynq supports TMDS signals so I can use any of High-Range I/O in PL ...
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1
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Understanding MIPI CSI-2 signals level
I am referencing an existing design that connects this camera through MIPI CSI-2 interface. I could just take this pinout and have it implemented on my custom board using same SoC used in the ...
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Efuse programing using XilSKey lib, Zynq UltraScale+
I'm working with Zynq UltraScale+ and using the XilSKey library for EFUSE programming over JTAG. I came across the JtagReadUltra function, which prepares a buffer (<...
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ZYNQ XC7Z010-3CLG400E - Can I use SPI MIO to EMIO?
This will be my first attempt to design PCB based on Xilinx Zynq device. The specific part number is XC7Z010-3CLG400E. My main objective is to learn how to design high speed peripherals including DDR3,...
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In Vivado Hardware manager, how can I (either by menu option or TCL script) read back the CRC from a programmed Xlinx/AMD 7-Series FPGA
With the old Xilinx ISE/iMPACT tools one could connect to an FPGA via JTAG, and then select a menu option to read out the CRC from the programmed part. This was also useful from an engineering ...
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signal rate error handling in FPGA
I am implementing a Manchester decoder for a serial input with rate 10mbps +/- 0.01% bit timing error. The sampling frequency is 160MHz +/- 50ppm.
Longest packet is 1526 bytes * 8 = 12208 bits. So ...
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1
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121
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Bin file in ZYBO FPGA (boot from SPI)
I am new to Zynq architecture. I want to run counter on ZYBO. I run it on PL using JTAG just by generating bitstream.
Now I want to create mcs/bin file and want to store it in QSPI and want my board ...
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Stabilizing ODELAY_VALUE related to IODELAY2 module in Spartan6 SLX9 FPGA Design for SDRAM Interface
I'm working on an FPGA design for the Spartan6 SLX9, which includes a memory controller for off-chip Micron SDRAM. To introduce a delay on the clock signal to the SDRAM relative to the Data/Command ...
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203
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How to use FPGA system clock for my design in vivado?
Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA.
I have ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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AMD/Xilinx SystemVerilog class variables dissapear in script vs. project simulaiton
I have asked this question on Stackoverflow but not answer yet. So, let me try EE stackexchange forum.
While scripting one of the SystemVerilog class-based testbenches I noticed that the testbench (...
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247
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Verilog: How do I assign multidimensional arrays as outputs in my module
I am writing my Verilog module in Xilinx Vivado. I am actually dealing with 2D arrays. I want to add elements from one array to another in the following way.
For Example:
...
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0
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52
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Simulating and verifying DDR3L clock
Context
I am working on a PCB that hosts a Zynq Ultrascale+ SoC and has 9 DDR3L SDRAMs (MT41K512M8DA) operating at 1866Mbps, and I have to verify the signal integrity of the DDR3L interface. I am ...
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How to Start Simulation (in specific turtorial) in Vivado with Custom FIR Using Xilinx DDS?
I’m following a guide (Here is the link to the guide:
https://www.hackster.io/whitney-knitter/dsp-for-fpga-using-xilinx-dds-with-custom-fir-f82447) for implementing a custom FIR filter in Vivado and ...
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1
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265
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How to see the connections of each flip-flop in Vivado RTL schematic view?
I am trying to make the design shown below which is basically a shift register:
When I elaborate this design in Vivado, it shows me the following:
How can I see which flip-flops the inputs and ...
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How do I initialise an Unpacked array in Verilog?
I need to initialize multiple lookup tables, for which I need a 12-bit array of possibly many indexes. An example:
reg [11:0] address[1:0];
For this, how do I ...
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Populating BRAM using a .coe file on Xilinx Alveo U280
I am new to the world of FPGAs.
I am using Xilinx Alveo U280. While performing a task in my research project, I tried to populate the BRAM with 0's but the simulation shows 'Z', 'ZZ', and 'ZZZZ' as ...
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1
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634
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Vivado Ethernet IP core licensing issue
I have a PL design in which I included a 10G/25G Ethernet Subsystem IP core from Xilinx configured with BASE-KR, AN/LT logic and FEC logic for Clause 74. When I try to generate the bitstream, I am ...
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How to change the FPGA supply voltage (VCCint and VCCBRAM) beyond recommended operating conditions on Vivado?
I am new to the field of FPGAs. The FPGA I am using is Virtex-7 VC707 -2 speed grade. In my research project, I am required to reduce the supply voltage (BRAM's specifically) to a low value, say 0.7 ...
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Why is Xilinx ILA's clock frequency required to be at least twice of that of JTAG?
In various places, it's mentioned that the frequency of the clock input to ILA module has to be at least 2.5x of JTAG frequency, otherwise ILA may not work properly.
Out of curiosity, I am wondering ...
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VDHL - Using multiple I2C devices with single IP
I need help with a design that I am currently working on. I am using a Spartan 3 that is on a custom board that checks 6 devices using I2C and these devices all have the same address so I am trying to ...
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Verilog/Xilinx Vivado Multidriven Net
I am trying to implement a TPU like SoC and seem to have a bug in one of my modules.
Here is the code for that module:
...
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139
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Artix-7 SATA implementation using LiteSATA won't initialize
I am trying to run the LiteSATA bench file provided for the Nexys Video (Artix-7 xc7a200t-sbg484-1). The board is new and does not have anything connected to it, and I am building / loading the ...
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Get Input Text from Console on MicroBlaze Softcore
My experience with writing embedded C is pretty limited so there will probably be a simple solution to this question.
I am using a Microblaze softcore on a basys 3 FPGA development board and will have ...
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What's causing this error in synthesizing and inferred latches warning?
I have two issues with my code:
This is the module that's showing an error in line 11 curr_state <= rst_n ? next_state : A; during synthesis:
...
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1
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How can I compare the speed of two algorithms implemented in verilog HDL without using FPGA?
I have implemented two 32 bit multiplier algorithms (Booth and Karatsuba) in verilog HDL. I wanted to make a comparison of the time taken by both algorithms to multiply same numbers. How can I do that ...
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1
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What does an .ngc file do in Xilinx ISE?
A couple days ago we were given our last project assignment at the HDL course at my uni. Among the files provided was a .ngc file and we were told to place it inside the project folder. It is supposed ...
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JTAG Programmer for Xilinx CPLDs
I have bought a Xilinx "Programmable Cable USB" so I can program the Xilinx CPLDs on my custom PCB. The PCBs are not ready yet. My question is, how do I test if this programmer is functional ...
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Atmel Micro-controller on a Xilinx CPLD board
This question is related to the CoolRunner-II Starter Board that was used to be offered from Digilent. See here for schematic. See here for the reference manual. Here is the block diagram for the CPLD ...
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Calculate Xilinx MCS PROM checksum (signature)
Is it possibly to calculate the checksum (or signature in Xilinx terminology) for a Xilinx MCS file myself, i.e. without using promgen.exe or any other Xilinx tools?
This question has been asked many ...
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"ERROR: [DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources." in newest Vivado
I am following section "Baseline Vivado project" in page 165-170 of book "Architecting High-Performance Embedded Systems: Design and build high-performance real-time digital systems ...
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Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?
What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.
At first I was thinking of configuring on-board DDR ...
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VHDL: Counter occasionally does not reset
I'm using ISE Project Navigator 14.7 with a Xilinx XC95144XL-5TQ100C CPLD in conjunction with a LM1881 video sync separator. I've also got a 14.3 MHz clock. I'm trying to generate VSYNC pulses in ...
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Can glitches in hardware be eliminated completely by using behavioural code instead of structural gate-level implementations?
If, for example, I implement a multiplexer in VHDL using logic gates, it may produce hazards, but if I use a higher level of abstraction describing the circuit in code, the simulation will not produce ...
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FPGA SPI controller ADC + posedge/negedge constraints
I want to implement the SPI controller for an ADC and have the following timing diagram :
I'm implemented an FPGA controller that works on posedge clock, detecting the data coming from DOUT pin (it ...
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1
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Communicate serial data with ethernet on Xilinx
Is it possible to communicate serial data traffic via ethernet (usually we use uart-usb for that purpose)?
I am talking about Xilinx Ultrascale+ based board [ZCU102, Avnet Ultrazed.]
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Problems in UART communication using Nexys 3 board
I am trying to send 1 byte of data from my Nexys 3 board to my PC using UART communication.
The problem is that whenever I try to view the data on RealTerm no matter my input (hard coded into the code ...
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1
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I am trying to implement ECDSA signature verification algorithm. I am facing errors in the synthesis part
I wrote a synthesizable Verilog HDL code in Xilinx Vivado to implement ECDSA Signature Verification. There are no syntax errors, but synthesis failed. The inputs I am taking are of 7 bits each - r,s,P,...
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