Can glitches in hardware be eliminated completely by using behavioural code instead of structural gate-level implementations?

This may change the behaviour of the VHDL simulation, but when you actually want to operate the circuit in an FPGA, both of them are going to be turned into (probably) the same hardware with the same glitches.

Since you are using Xilinx tools, you have the ability to simulate the programmed FPGA, rather than simulating the VHDL code, and you might see the same glitches there too.

Can glitches in hardware be eliminated completely by using behavioral code instead of structural gate-level implementations?

No. You must check the resulting hardware, simulate the final results (not the VHDL code) and use constraints if needed.

If, for example, I implement a multiplexer in VHDL using logic gates

You don't actually implement it, you describe it when using VHDL or Verilog. It is the synthesis tool that actually implements the hardware that matches the description.

For example, consider this MUX 4x1 interface:

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4x1 is
    port(D3, D2, D1, D0 : in std_ulogic;
         SEL : in std_ulogic_vector(1 downto 0);
         MX_OUT : out std_ulogic);
end mux4x1;

and these 3 implementations:

architecture my_mux4x1 of mux4x1 is
begin
    MX_OUT <= D3 when (SEL = "11") else
              D2 when (SEL = "10") else
              D1 when (SEL = "01") else
              D0 when (SEL = "00") else
              '0';
end my_mux4x1;

architecture my_mux4x1 of mux4x1 is
begin
    process (D3, D2, D2, D0) is
    begin
        if (SEL(1) = '1') then
            if (SEL(0) = '1') then
                MX_OUT <= D3;
            else
                MX_OUT <= D2;
            end if;
        else
            if (SEL(0) = '1') then
                MX_OUT <= D1;
            else
                MX_OUT <= D0;
            end if;
        end if;
    end process;
end my_mux4x1;

architecture my_mux4x1 of mux4x1 is
begin
    MX_OUT <= (SEL(1) and SEL(0) and D3) or
              (SEL(1) and (not SEL(0)) and D2) or
              (not(SEL(1)) and SEL(0) and D1) or
              (not(SEL(1)) and not(SEL(0)) and D0);
end my_mux4x1;

All 3 descriptions are implemented with a single Lookup-Table (LUT6) by Vivado for a Xilinx FPGA.