Skip to main content
Electrical Engineering

Questions tagged [high-speed]

Ask Question

High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

396 questions
Newest Active Bountied Unanswered
Filter by
Sorted by
Tagged with
0 votes
1 answer
196 views

I am designing an adapter board for a camera which is an original device with Gigabit Ethernet interface. The previous version of the adapter board was using LAN7500 and transformer as a USB dongle ...
Sławek Małkowski's user avatar
  • 1
2 votes
5 answers
1k views

I have a question. Usually, in normal communication interfaces such as I2C, SPI or even normal GPIO interfaces, we don't associate them with impedance matching. But for certain signals (I don't know ...
user avatar
0 votes
1 answer
161 views

New to PCB Design and layout. While routing bypass caps, I instinctively give each bypass cap its own via to the ground plane. What would be the disadvantages of having two (or more) bypass caps share ...
Novak's user avatar
  • 1
0 votes
2 answers
95 views

I'm designing a drone controller board and a power distribution board. The power distribution board will supply the controller board, and up to 4 (Electronic Speed Controllers)ESCs, from a 4S-6S LiPo ...
Chance K's user avatar
  • 151
1 vote
3 answers
3k views

I am trying to get high RPM output from my stepper motor, but no matter what I try I can't get it to spin more than 65,000 steps/sec. I have tried many combinations of settings, drivers, power supply, ...
Harsh Dobariya's user avatar
  • 111
0 votes
0 answers
180 views

I want to do a MIDI Controller which uses 15 MHz SPI between a Teensy 3.6 and 74HC595 / 74HC165 Shift Registers to read a button Matrix. The code is finished and the PCB would be the next step. I have ...
Didda's user avatar
  • 1
2 votes
1 answer
2k views

In many places I have seen that an AC termination scheme is recommended for high speed clock termination. What is the reason for choosing this scheme? For AC termination, can a capacitor be connected ...
Sumama Hahsir's user avatar
  • 21
0 votes
0 answers
74 views

I know this question depends on the component but let's take this one for example : https://www.nexperia.com/products/analog-logic-ics/asynchronous-interface-logic/voltage-translators-level-shifters/...
Propolis's user avatar
  • 141
3 votes
1 answer
285 views

I was reading the datasheet for an Ethernet interface layout from NXP and I found they didn't use a reference plane in the region where they routed the differential pairs. I couldn't understand why ...
arisk4's user avatar
  • 103
5 votes
1 answer
229 views

A continuation of this project, that I hoped would be done and working by now. The problem this time appears to be that the circuit is too slow. The desaturation/grayscale and attenuation seem to ...
AaronD's user avatar
  • 6,014
0 votes
2 answers
253 views

I have a four layered PCB with two major high frequency component placed on the top layer. One is JN5169 and other is SE2431l (front end module), both operate in GHz. While evaluating the circuit (...
Akanksha Upadhyay's user avatar
  • 11
3 votes
1 answer
805 views

I am investigating PCB stack-up. Everywhere I have seen it says to route signals on adjacent layers orthogonally to reduce the coupling. I have two questions: How does orthogonal routing reduces the ...
Confused's user avatar
  • 4,055
0 votes
1 answer
512 views

I am learning about computer architecture and organization. I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
Anshul Gupta's user avatar
  • 375
0 votes
1 answer
569 views

I am new to high-speed PCB design. I was studying controlled impedance traces from the internet with the help of various documents. Everywhere it says controlled impedance traces need a reference ...
Confused's user avatar
  • 4,055
1 vote
0 answers
96 views

We’re working on a product that makes use of USB HS, and are having some connection and consistency issues. Originally, our product was USB FS-based and we had no connectivity issues; with this second ...
snoopledorf's user avatar
  • 11
0 votes
1 answer
132 views

The current design uses a Micro B connector for the USB 3.0 connectivity. Unfortunately, this connector is susceptible to mechanical stress if the PCB is not handle with care, which results in ripped ...
Mr.Y's user avatar
  • 325
0 votes
2 answers
2k views

I am a chemistry student and I am beginning to realize that I have fallen into a EE rabbit hole.. I am trying to create a PCB (digital audio delay unit) from a schematic which includes a SDRAM, this ...
J.Doe's user avatar
  • 356
3 votes
1 answer
203 views

I have a twisted pair input to the IN+ and IN- pins of the MAX9278 deserializers. The Parallel data output of the deserializer consists of 4 LVDS data channels and 1 LVDS Clock channel to a 3.1" ...
user avatar
2 votes
0 answers
780 views

According to Microchip's document Implementation Guidelines for Microchip’s USB 2.0 and USB 3.1 Gen 1 and Gen 2 Hub and Hub-Combo Devices, the Superspeed differential pairs should be length matched ...
Rocketmagnet's user avatar
  • 28k
1 vote
1 answer
850 views

I need to drive an ultrasonic transducer with a high center frequency (25 MHz) using my function generator that outputs a 25 MHz sine wave at only 5 Vpp. The problem is that the transducer needs at ...
Landon's user avatar
  • 187
2 votes
2 answers
984 views

in many application notes for processors in a BGA package I see a declaration that you could fully fanout the bga using only 4-6 layers and almost no HDI technology like microvias, burried vias even ...
Nyquist's user avatar
  • 21
1 vote
1 answer
2k views

USB 3.0 and USB 2.0, pci signals, Why its always recommended to route at 85E impedance and not 100E impedance? Below are the signals to be routed at 85E D− (USB 2.0 differential pair) D+ (USB 2.0 ...
Ananthesh's user avatar
  • 285
0 votes
0 answers
202 views

I'm using it for my work in Hyperlynx SI to test high-speed signals. This is a general question but I read somewhere that the simulation in high freq could make a problem to identify some peaks in ...
Knowledge's user avatar
  • 553
0 votes
0 answers
100 views

I have a query regarding selection of SerDes ICs. I need to select an IC which is compatible with 3 formats - 24bits, 32bits and 27bits. MAX9275 - Just a sample IC datasheet in the MAX SerDes GMSL ...
user avatar
8 votes
2 answers
8k views

I'm designing an open source USB Type-C Switch (KVM Style), and I started to route the USB 3.x SuperSpeed+ and USB 2.x HighSpeed differential signal pairs on the PCB. The switch will have 2 input + 1 ...
bluetiger9's user avatar
  • 225
2 votes
2 answers
677 views

I am designing a board with USB 2.0 and Ethernet 10/100Mbps. I found this layout guide with very helpful information. In the layout guide, at p. 34 (Table 7), it says that the minimum spacing between ...
Cristian M's user avatar
  • 347
2 votes
3 answers
297 views

I found this article that describes the specific impedances that single/differential traces must have for high speed signals (using microstrips). But what happens to these impedances beyond the ...
Cristian M's user avatar
  • 347
2 votes
2 answers
3k views

I'm very confused that dielectric constant should be selected high or low to design high-speed boards. It can be compared with FR4 material, dc ~4,6.
yardi's user avatar
  • 96
3 votes
2 answers
2k views

I am designing a flexible PCB to carry two types of differential signals. One is about 1.2Gbps 100R differential impedance, while the other is only 3Mbps, with much more tolerance on the impedance. ...
Rocketmagnet's user avatar
  • 28k
0 votes
1 answer
927 views

I am trying to use below circuit for convert 24VDC high speed pulse to 5VDC pulse that can interface to a stepper driver IC. I have used 6N136 opto-coupler and according to its datasheet it can handle ...
user_fs10's user avatar
  • 891
1 vote
2 answers
612 views

I'm designing a PCB circuit for an amplifier to amplify a pulse with a rising time of 1 ns about 100 times. I decided to use the Analog Device AD8000 as op-amps. This is the schematic of one amplifier....
Hyunmin Yang's user avatar
  • 11
1 vote
1 answer
66 views

I am designing a board, 4 layer with a ground plane. In my current layout, the ground VIA of an oscillator IC is very close in proximity with the ground VIA of a high speed IC. Is there a chance that ...
Mr.Y's user avatar
  • 325
0 votes
1 answer
253 views

I am little bit confused over impedance matching when dealing with high-speed digital I/Os. I would like to share some perspectives in hope to clarify a few things. Let's consider a digital output ...
Mr.Y's user avatar
  • 325
0 votes
0 answers
100 views

Designing a circuit (PCB) operating at low frequencies is fairly straight forward. However, my design includes a simple RF frontend. The frontend consists of usual componenents on a PCB (SMA connector,...
divB's user avatar
  • 1,362
1 vote
2 answers
683 views

I am planning a stackup for 2x Ethernet phys. The chip requires a few different supply voltage levels: I/O Power 3V3 (3 pins) and Analog Supplies: VDD2V5 (2 pins) and VDD1V0 (4 pins). Each pin has ...
kch78's user avatar
  • 11
0 votes
0 answers
260 views

I am designing a voltage multiplier with 5 to 10 stages. I have this circuit where I run a transformer at 450KHz and feed the output to the voltage multiplier. Is it a good idea to use thin film ...
Deadpool's user avatar
  • 65
6 votes
1 answer
1k views

Micron's Technical Note TN-40-40: DDR4 Point-to-Point Design Guide, page 19, says (emphasis mine): Timing Budget Suggested practice is to look at the design from a timing budget standpoint to provide ...
mFeinstein's user avatar
  • 4,413
6 votes
3 answers
1k views

UART is great to transmit log data from a DUT to a PC. However, it is not fast enough. There are many newer things like USB, PCIe e.t.c that can transfer a lot more data and also use serial transfer. ...
gyuunyuu's user avatar
  • 2,347
0 votes
1 answer
220 views

Imagine you are routing a large number of single ended high speed traces through a long narrow gap on a PCB. Lets say these are ultra-high speed SD signals, so a 208MHz clock. The traces should be ...
Matthew T Watson's user avatar
  • 143
1 vote
0 answers
300 views

I am working on a PCB layout on a very space constrained, 4-layer board. On the board is a MIPI-output image sensor (1 lane) which go to an FPGA. Layer 1: Image sensor Layer 2: Full Gnd plane Layer 3: ...
Rocketmagnet's user avatar
  • 28k
5 votes
3 answers
4k views

I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped. I've never done DDR routing and went with SP605 Xilinx ...
batyastudios's user avatar
  • 143
3 votes
0 answers
750 views

I’m building a simple SBC based on Allwinner A33 for my undergraduate final project, includes two x8 DDR3 chips. I’m going with 6 layers JLC2313 Stackup 1.2mm thickness (cost reasons). It’s my first ...
TIdo's user avatar
  • 31
1 vote
0 answers
129 views

I've noticed when adding an external attenuator between PCB and the scope (1MOhm) that it is placed in this manner: PCB -> SMA Socket -> SMA Cable Plug -> SMA Attenuator -> SMA-to-BNC -> Scope Why ...
Azaxa's user avatar
  • 85
1 vote
1 answer
452 views

I read since a long time but never had an account, now its my turn to ask a question on here: I have an idea but currently unsure if that works technically or if it is good design: 1st (Top Layer) : ...
Jeres's user avatar
  • 141
0 votes
1 answer
827 views

I need to create a circuit that will have many cameras. Possibly the OVM7692. I will connect this array to my host processor via DVP. The cameras are controlled via SCCB which seems to be a name that ...
RWeiser's user avatar
  • 159
6 votes
1 answer
4k views

I'm reading TI's recommendations on routing high-speed signals. Most of the guidelines are common sense, but there's one guideline that I haven't read before: It recommends completely removing the ...
比尔盖子's user avatar
  • 7,947
1 vote
0 answers
516 views

I'm doing the layout of a high-speed (Multi gigabit) system based on an FPGA with more than a thousand BGA pads and 0.8mm pitch on a 10-layer board. I'm using via in pads that will be copper-filled ...
Abdella's user avatar
  • 2,682
1 vote
0 answers
52 views

A design using high speed ADC is to be carried out involving an FPGA as the master device. To simplify the prototype phase, a daughter board with the ADC shall be designed and connected to the FPGA ...
quantum231's user avatar
  • 12.4k
2 votes
2 answers
586 views

For some test equipment I have an LVDS line running at 100 Mbps. I would like to make an Arduino Due (because I use this for other monitoring in the test) detect activity on the LVDS line. Using a (...
pmbdk's user avatar
  • 21
2 votes
1 answer
965 views

The FPGA Mezzanine Card is a connector intended for use with daughter boards that have high frequency components. Thus, if one was to use a 100MHz+ daughter board, it would require use of either FPGA ...
gyuunyuu's user avatar
  • 2,347

1 2 3
4
5
…
8