I’m building a simple SBC based on Allwinner A33 for my undergraduate final project, includes two x8 DDR3 chips. I’m going with 6 layers JLC2313 Stackup 1.2mm thickness (cost reasons). It’s my first DDR3 design and I have a lot of questions.
Their website/field solver suggests 14 mil track on stripline and 5.7 mils on microstrip for SE50 ohms impedance. That’s super thick.
I was wondering if I can use SE60 ohms and 120 ohms for differential pairs on DDR3 (That’ll be 9.4/3.8 mils).
I’ve included the stack up. L1=> Signal, L2=> GND plane, L3=> Signal, L4=> Signal, L5=> Split Power, L6=> Signal. The prepreg (Dk=4.25) between L3 and L4 is just 5 mil (0.127mm) in thickness. Would that cause a lot of crosstalk? Was planning route ACC on L3 and data banks on L4. Would keeping almost minimum intersection help me out here? I will reference it to the adjacent layers (GND,VDDQ) , separated by cores with a thickness of 14.37 mil (0.365mm).
Any suggestion on ddr3 layout and layer utilization, especially with JLCPCB’s 6L stack up? (Included a preliminary component placement).
About DDR3 termination, BBB, most of the boards from Bpi, Olimex, OrangePi and even Rpi seems to be termination only the DRAM clock. What about ACC group?
DRAM reset signal, Is it a pull-up or down? Is it SoC specific? DRAM_RESET is active low, but I've seen a couple other designs utilizing a pull down. I’m using H5TC4G83AFR-PBA/PBC DRAM chips.
I understand differential pair’s impedance can be seen as two single ended TL’s impedance coupled with a gap. I’ve tried iCD stackup planner and can’t quite get the bang-on 120 ohms differential geometry right on JLC’s stackup (aware of the 10% tolerance), same story with their website (they seem to be using Si8000). So, is it weird to maint
ain 60Ohm SE and 100Ohm Differential for DDR3 signals?
I highly appreciate any inputs and suggestions. Thanks a lot
