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Questions tagged [high-speed]

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High-speed design deals with designing circuits which are working at high frequencies where side-effects like path inductance gain significant influence.

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I'm using HyperLynx to emulate my STM32MP157AAA3 small form factor system board with DDR3-1066 memory. When I use DDRx batch simulation: I confirmed that my ODT model is configured correctly. Use 48 ...
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I will have two gate inputs A and B to be ANDed; and so far I tried two AND gates: the ideal gate of LTspice and 74HC08 using 74HC library: The 74HC08 cannot respond the transitions of inputs but the ...
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I am designing a device where 100 slaves are connected to a master with SPI bus and the bus must be isolated on each node. Speed requirement is 1 MHz and cables are fairly short (about 10 cm between ...
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In my product, PCIe is just used for data transmission between SOC and Wi-Fi chipset. It's not used for any other purpose. Is compliance testing necessary for this scenario? What type of SI ...
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I am trying to understand the need for termination resistors in DDR2/DDR3 designs and I have seen some Max 10 dev kit boards that don't terminate the address lines with 50 Ω terminating resistors. ...
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We normally parallelly terminate with a matching (50 Ω) resistor in high-speed designs. Normally, the load/receiver is high impedance, but if we terminate it with a 50 Ω resistor, wouldn't the whole ...
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Given the image below, what would be the best place to place the PHY and Magnetics, (connectors can move)? I appreciate that Ethernet best design practices are not being followed here, but given this ...
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I was wondering how one finds the total return loss between transceivers. In particular, how return losses of connectors are added. Say if I have two connectors with a return loss of -10dB. How do I ...
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Via delay is different between layers, it's also different between the top and bottom layers and say top and an inner layer. Altium only provides one delay for each via, which means if you switched ...
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In Ali express, I found the following high voltage small generator for fun. One transistor, one single coil, 2 caps and 2 resistors (not sure if the leds are an essential part of the circuit). The ...
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I have seen the answer for when to consider PCB trace as a transmission line in many places. Typically, if the signal pulse rise time is ‘small’ compared to the time it takes for the signal pulse to ...
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Currently I'm working on a PCB that doesn't really need to be 6 layers, but I had to manufacture this project with my other 6 layers. Here is a problem, I have a blank layer; no signal or anything on ...
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I am working with this Ethernet PHY. This is the - MAC Controller IC. I'm using the RMII interface. When Renesas send the DHCP request, I have the feeling (not 100% sure, I will try to find it out) ...
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I'm designing a CAN bus interface for a PCB I'm working on. CAN and high speed/long distances are new to me, so I have a list of concerns about my design ideas, and I would appreciate someone with ...
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Is the below waveform that I am getting in TX- line of Ethernet (PHY Used - LAN8700) correct? (Waveform obtained without connecting the LAN cable). Using RMII mode in the PHY. R801 & R803 (pin 1) ...
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I've 2 questions on Ethernet design: Suppose I am using a current mode Ethernet PHY which requires termination resistor of 49.9 ohms to VDD on the Ethernet differential lines. Can I increase the ...
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I'm working on a constant power source for some heat output science experiments using Arduino, low Rds N-MOSFETs and dead-time capable half bridge MOSFET driver. I plan to run this at around 30 kHz ...
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If you have length matching on the inner layer of 4 layer board: Do you need any minimum or maximum distance to the adjacent layers above and below? Are there any rules of thumb? Also is there any ...
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What is the purpose of this pad, located between the PCB in the picture and a wifi card? It is completely enclosed in Kapton tape and there are no exposed grounds on the PCB below, on the bottom of ...
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I have been working on this new project where I need to include Ethernet. But the microcontroller of my project doesn't have any Ethernet PHY included (no MII, RMII, GMII, etc.) So, I am instead using ...
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I have a system which transmits 1 Gbps single lane MIPI video over several flex circuits. Where each flex circuit connects to its neighbour, I have placed a MIPI repeater chip: SNx5DPHY440SS. At the ...
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I've read numerous posts advising that trace length must be kept short on a high speed board to reduce the effects of impedance. If my traces are routed through a pin header that has an IDC ribbon ...
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I have a custom board with STM32H743VIT6 connected to an external USB HS PHY, the FUSB2805MLX. I am trying to run a bare minimum example setup in STM32CubeMx. Just including a USB HS connection and ...
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I am having trouble understanding where manufacturers are coming up with their length matching requirements. For example, I am looking at length matching for RGMII between a MAC and PHY. My ...
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Hello community member, I have a 4 layer PCB. At what data rate should I consider via back-drilling? Also do we back-drill 3 layer flex PCB? Thanks.
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I'm working on a Frequency Response Analyzer based around an Altera/Intel FPGA. I'm using an older Cyclone V educational eval board I got for cheap from my university. The only real GPIO I can use are ...
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I'm making a high-speed transceiver design and want some direction regarding layout of trace length from P to N. The speeds will be up to 12.5Gbps. I have been informed by a equalizer manufacturer ...
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I am working on a 2 layer board with ground and power layer on top and bottom and I have reached a single point where the 2 layers are limiting my design. It is regarding SPI signals that would be ...
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Many application notes (like this one) advise series resistance to be added on the clock line, close to the source. I do understand that this resistance is added there to match the source impedance to ...
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I am designing a pcb using LDDR3 for the first time. There are some questions that confuse me. Should I match all DQ,DQS,DM signals with equal length? Should I match the common address CA signals ...
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I'm working on implementing a PCIe 2.0 x2 system on a with a Xilinx Ultrascale. Reading through the PCIe 2.0 specification it requires 75-200nF AC coupling capacitors on the TX lines coming from the ...
Mitch's user avatar
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I'm finalizing the routing for an eighteen-layer board that requires many, many differential-pair traces to run at speeds up to 16 Gbit/sec. (FYI: 100 Ω impedance, Isola I-Speed cores and prepreg.) ...
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Sorry if this question is dumb, I'm still a student... Anyways, I was looking at a design of a high voltage differential probe on the web and was wondering what is the purpose of the capacitors seen ...
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I'm working on an eighteen-layer board right now. Almost all of the signal layers have high-speed, single-ended traces that should run up to 15 gbit/s. The vias for these high-speed traces will be ...
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Can anyone tell me what the purpose of split termination is in a differential pair? If you look at the LVDS article on Wikipedia, you'll see the 100 Ohm termination resistor in parallel across the two ...
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When designing a power supply for a digital circuit such as a CPU or microcontroller, you often want to ensure that the supply does not exceed some threshold when the load is switched from minimum to ...
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In a design I'm working on, I have a 100Mbps differential signal traveling from a chip on one PCB to a chip on another PCB. For various reasons, I can't make the differential impedance the same on ...
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I was watching the below video from Rick Hartley. In this he says more than signal frequency signal rise time is more problematic. A signal with rise time in the range of picoseconds and frequency in ...
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Cutoff frequency is often measured and presented in academic papers, for example, for high electron mobility transistors. How is this defined exactly? Is it defined as a frequency at which the current ...
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This question is related to Differential pair length matching considering phase. According to Microchip's document Implementation Guidelines for Microchip’s USB 2.0 and USB 3.1 Gen 1 and Gen 2 Hub and ...
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In my project my customers wanted a 2 port 2 lane PCIe switch and The switch is occupying more space than I can allocate on the board, Before I can ask my customers to get approval on using an ...
Voldemort's user avatar
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I am designing a DDR3 interface to a Xilinx Kintex Ultrascale FPGA. The FPGA is connected to two separate DDR3 chips which share address, command, and control lines using flyby topology. I've attached ...
imnotarobot's user avatar
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I am referring to a microstrip PCB transmission line. I simulated the crosstalk situation using Hyperlynx. Please see the below circuit: I kept increasing the trace length and measured the crosstalk ...
Confused's user avatar
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I was making a PCB design in which I need to connect a high speed (1Gbps) DSI bus to a FFC connector. The problem is I need to test 2 displays which have different types of connectors so I was ...
Ankit Sharma's user avatar
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I am designing a "simple" current source using an op-amplifier. My question is why is my fall time looking like that: What do I need to reduce the fall time? Here is the schematic:
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I am working with Logic Gate Output Optocoupler. I have tried removing 15pF capacitor but it didn't made any difference. On output port it is generating noise Any help would be appreciated..! Thanks ...
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I am doing the integration of an aircraft device that uses Ethernet 100BASE-T as its main communication line. The manual says the device comes with its own testing cable which is approximately 2 feet ...
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I'm designing a little bridge PCB to convert USB-C to FFC Connector (iPex EVAFLEX 5-VS). I'm following the next configuration (the cable that is been replaced was USB-C to USB-A) for legacy cables, ...
Juanma's user avatar
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Lets say there is a black-box which gives a voltage output that evolves temporally from nV regime to few 100s of μV regime, in very short time scales. i.e the signal evolves from nV to μV in ns with ...
eigenvalue's user avatar
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I am trying to find more information about data oversampling for transceivers when grabbing/sending a lower speed signal. I am looking into building a fully compliant HDMI 1.4b fpga core, and have ...
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