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I'm working on an eighteen-layer board right now. Almost all of the signal layers have high-speed, single-ended traces that should run up to 15 gbit/s. The vias for these high-speed traces will be backdrilled to be a total length of 23 mil, keeping the via stubs no longer than roughly 1/20th of a wavelength. However, to keep costs down, there are only two drill pairs, meaning that a high-speed signal may only need to travel 3 mil down a 23 mil via. In this worst-vase scenario, the via would have a 20 mil stub, which my calculations indicate is less than 1/20th of a wavelength. This will minimize reflection caused by the stub.

However, I am unsure how to calculate the via impedance of stub. According to the Saturn PCB Toolkit, via height will non-negligibly affect impedance at such high frequencies, but this can easily be adjusted by changing the anti-pad diameter. But should my calculations account for the length of the via that the signal would actually travel (3 mil), or should the calculations still account for the entire 23 mil of via height?

Calculating antipad based on via signal length:

Calculating antipad based on via signal length

Calculating antipad based on total via height:

Calculating antipad based on total via height

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    \$\begingroup\$ Won't the untraveled portion of the vias create a small stub on both ends of the via? And won't that small stub just add some capacitance to that part of the trace, that needs to be accounted for when calculating the impedance of that part of the trace? \$\endgroup\$ Commented Oct 26, 2021 at 19:57
  • \$\begingroup\$ Guess what I'm saying is what you have is transmission line->small cap -> 3 mil via -> small cap -> trans line? \$\endgroup\$ Commented Oct 26, 2021 at 19:59
  • \$\begingroup\$ The signal would be traveling from the top layer into some internal layer, which could potentially leave a stub of up to 20 mil. \$\endgroup\$ Commented Oct 26, 2021 at 20:05
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    \$\begingroup\$ @wisner at this frequency, using Saturn PCB for via modeling is kind of impressive and pitiful. Above 3-5GHz you need a 3D full-wave analysis software to model via impedance. Also at your speed you also need to model stitching vias, I don't really know how you do it. Doing 18L board with 15Gbps signal means you have some money, so either you buy a simulation software, either you spend your money on multiple board spin. Hyperlynx got its price down for few years now, and you can still rent it. You also have Simbeor that is relatively cheap for SI simulation. \$\endgroup\$ Commented Dec 15, 2021 at 22:00
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    \$\begingroup\$ @wisner I did several design with 10G/12.5G without much simulation tbh. But currently our boards use a Intel/Altera via structure (with antipad) given in AN766 (high-speed design guidelines). At least you can try to rent ou buy a limited time license to keep cost low and simulate a lot of structure that you could reuse after. That need a lot of preparation to be useful. \$\endgroup\$ Commented Dec 21, 2021 at 18:17

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I would input the physical parameters of the vias once back drilled.

Try another program and then compare the 2 results.

It's an interesting question.

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    \$\begingroup\$ Is there another free program you would recommend? I'm afraid I don't have access to any 3D simulation tools. Could you make a suggestion for a free program? \$\endgroup\$ Commented Oct 26, 2021 at 19:20
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    \$\begingroup\$ I haven't been simulating RF structures since 2016 and I actually don't know if any free or open source simulator. You may download a free trial version of ADS or Microwave Office. \$\endgroup\$ Commented Oct 26, 2021 at 19:59
  • \$\begingroup\$ yes, them simulation programs are quite expensive \$\endgroup\$ Commented Oct 30, 2023 at 17:53
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I think the trick to answering this question on the back of a napkin without fancy simulation tools is to consider the "relevant feature size".

In his book "Signal Integrity in Practice" (my reference for this answer), Donald Telian explains how one can disregard in-line features of certain lengths depending on bit rate (or more accurately symbol rate/baud). Features smaller than this length can be considered a lumped model. The third assumption of a lumped model is "Signal timescales of interest are much larger than propagation delay of electromagnetic waves across the lumped element." . Through back-drilling, you have reshaped the via to look approximately like an in-line feature. So now the question is, is it of relevant feature size?

The rule of thumb derived in the book is (0.6 * UI [ps]) [mil]. In words, that is "the length of a relevant feature size in mil is anything greater than 60% of one unit interval in picoseconds".

Your signal is 15 Gbps. One UI is 66.6ps. 60% of that is 40mil. Your 23 mil via is probably fine from an impedance discontinuity perspective!

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