Skip to main content

Questions tagged [jfet]

Junction Field Effect Transistor - A transistor whose channel is modulated by the application of an electric field that is the depletion region of a reversed biased diode that forms the gate electrode. Characteristic features of the device are low noise and low gate capacitance.

Filter by
Sorted by
Tagged with
2 votes
1 answer
153 views

I am designing a differential pair that is connected to a current mirror. I have calculated the drain resistors of the differential pair to draw around 16.5 mA and achieve a gain of 20 dB. When I ...
Dinkle Bob's user avatar
2 votes
1 answer
105 views

simulate this circuit – Schematic created using CircuitLab I am trying the understand the working of a P-JFET. Why is the behaviour strange for Case-3? Is it a simulation issue?
Dynamic_equilibrium's user avatar
2 votes
1 answer
64 views

Why are there two curves for transfer characteristics of MMBFJ270? Does it mean drain current can be bi-directional based on VDS - If so, I assume a typo in VDS parameter? Or does it refer common-...
Dynamic_equilibrium's user avatar
2 votes
2 answers
255 views

I’m having trouble with a small JFET amplifier stage after raising the supply voltage from 9 VDC to 24 VDC. The circuit originally worked fine at 9 V, producing a clean sine wave. With 24 V, the top ...
Aj2's user avatar
  • 31
1 vote
0 answers
79 views

Dear friends please help me to sorts this out. I have attempted to design a simple CS type amplifier for 27 MHz based on 2N5486 JFET. Pretty soon I realized that the 15 pF of input capacitance of my ...
Star REB 7's user avatar
3 votes
3 answers
109 views

I'm trying to understand the physics of a JFET in saturation, but books are contradictory. Some say that the depletion regions meet, pinching off the channel, but this is not a barrier to the ...
Ken Shirriff's user avatar
  • 3,207
2 votes
2 answers
187 views

I'm simulating an JFET multiplier circuit in Proteus based on a 2N3819 and an LC tank oscillator, my goal is to upconvert the FM signal centered in 100 kHz to a higher frequency (200 kHz) My attempt ...
Pedro Errazuriz's user avatar
1 vote
1 answer
137 views

After lots of fiddling with LTspice, I finally made a guitar pedal circuit that I am pleased with. I swept the potentiometers and all works fine. Output is behaving as expected. (I have marked the ...
Mosteanu Tudor-Radu's user avatar
3 votes
1 answer
120 views

I have been working on paper with JFETs for a while and finally got fed up and decided to go digital. I plotted a circuit of an input buffer using a 2N5485 JFET that I know works in real life and got ...
Mosteanu Tudor-Radu's user avatar
0 votes
1 answer
118 views

I saw in multiple Colpitts oscillator circuit a 1N914 diode from gate to GND. Is that how one can protect the gate of an JFET? My circuit:
sfsdfsd sds's user avatar
3 votes
1 answer
79 views

I am working with a circuit design that I have never seen before - my understanding is that is derivative of an audio signal amplification circuit, but the history is unfortunately lost to time. We ...
lopp's user avatar
  • 33
4 votes
3 answers
238 views

I am working on the AGC circuit below and was recently made aware of the fact that Vgs(off) varies widely for most JFETs including the JFET I was planning to use in my circuit J113 which has a minimum ...
CMH12's user avatar
  • 482
2 votes
1 answer
95 views

If the \$V_\text{GS}\$ is constant, the graph, drain current is as shown. If \$V_\text{GS}\$ varies, the drain current is as shown My question is, what actually is a saturion region for MOSFET? Why ...
user avatar
6 votes
2 answers
393 views

I have a bunch of J112 JFETs and would like to use them for high impedance input stage, but I'm a bit confused because the datasheet says that its Idss should be about 5 mA, but when I measured it, I ...
Triangle's user avatar
  • 103
4 votes
2 answers
214 views

I am reading Semiconductor Devices — Theory and Application (Fiore) about JFETs in chapter 10 and there are two drain current equations shown that do not agree with each other. The first equation is ...
Phill Donn's user avatar
8 votes
2 answers
1k views

I am studying how the bypass circuit of the Tube Screamer pedal works. It is dependent on two JFET transistors that are used as switches. I am not great at understanding JFETs as switches, as I have ...
Juan Aldrey's user avatar
0 votes
0 answers
80 views

This is regarding a cheap Pmod I2S2 ADC and DAC (connected to an STM32F407G-DISC1) that uses a Cirrus CS5343 ADC. Now, as best as I can tell from the CS5343 data sheet, the \$ V_{PP} \$ of the input ...
robert bristow-johnson's user avatar
2 votes
3 answers
631 views

Below is a simple JFET Clapp Oscillator, which works quite well. It starts oscillating at around 40us and gets into clean, stable oscillation by 100us: When I replace the J309 JFET with a more ...
SRobertJames's user avatar
  • 1,379
1 vote
2 answers
279 views

How does the circuit below oscillate? It seems to have |gain| < 1 at its oscillation frequency of 2.25 MHz, yet it oscillates there. My analysis: The DC path is through L4 only, allowing a bias ...
SRobertJames's user avatar
  • 1,379
2 votes
1 answer
196 views

I have a "JFET enhanced" op-amp circuit shown below: "JFET Enhanced" op-amp circuit Similar to the circuit used in the TI app note: App Note The circuit looks stable in SPICE with ...
Chris192's user avatar
1 vote
2 answers
124 views

In the circuit in this 1st picture, Rs resistance is bridged with C3 capacitor, so Rs is disabled when analyzing ac. but in this 2nd picture there is a capacitor bridging the Rs resistor, but we draw ...
softcalculate's user avatar
0 votes
1 answer
105 views

Pictured is a PIR (passive infra-red) sensor hooked up to a JFET. The diagram is from these design notes, which describes the workings of the PIR sensor as: ...
cornelius's user avatar
  • 265
0 votes
3 answers
336 views

I designed a microphone amplifier like in the simulation image below. The images of it in real life are also below. The microphone is a JLI2555. The input voltage used in the simulation is 1mV. When I ...
LEXOR AI's user avatar
  • 539
0 votes
2 answers
213 views

The task is to derive sinewave (of higher frequency) chopped by step-function (also periodic but of lower frequency, i.e. several periods of sine wave are placed in that pulse). So I have a sinewave ...
Sombercy's user avatar
1 vote
1 answer
381 views

the operating condition of JFET in saturation is stated below from this website. Vp stands for pinch-off voltage in the article. But after reading this post shouldn't Vp change to Vthreshold in Vds ...
Jack Huang's user avatar
2 votes
0 answers
180 views

I have been trying to learn how JFETs work. The first amplifier that I read about was the CS amplifier: I found that for a typical common source amplifier configuration at low frequency, the input ...
Analog's user avatar
  • 417
0 votes
0 answers
94 views

I have a question about the following homework exercise. I have no clue what B means in this equation. I could not find meaning of it in google nor in the books. Could someone link me a resource or ...
T1P0Z's user avatar
  • 107
1 vote
3 answers
383 views

In my first realization of a common source JFET preamplifier, I encountered a rather predictable problem but for which I was unable to find any documentation: the power supply ripple and noise are ...
boromyr's user avatar
  • 53
0 votes
1 answer
163 views

I have an H-bridge connected to a piezoelectric ceramic transducer which feeds it 40kHz 38V AC. After 3 full oscillations, it is stopped and it starts waiting for an echo, which is probably going to ...
epicMan123's user avatar
0 votes
0 answers
128 views

I am looking at datasheet of the MMBFJ175 P-Channel JFET (Datasheet). There is one graph were I have a really hard time to understand, what it means and how to interpret it. . IDSS doesn't have a ...
Lucas's user avatar
  • 565
0 votes
2 answers
372 views

I've recently built a resettable integrator board which uses a low-drift JFET op-amp and a sample and hold chip. The sample and hold amplifier datasheet showed a resettable integrator configuration ...
sam.schimanski's user avatar
3 votes
3 answers
437 views

I have two questions about the following JFET-BJT amplifier circuit. This circuit is presented and analyzed in paragraph 3.2.3D of the Art of Electronics. The book comes up with the following design ...
Pim Borman's user avatar
1 vote
0 answers
85 views

I am reading "Practical Electronics for Inventers" 4th edition and came across this circuit. As I understand, for a JFET, current will flow from drain to source for a n-channel (opposite ...
Qubit's user avatar
  • 175
2 votes
1 answer
490 views

I am unsure how a differential-input JFET amplifier in a closed-loop can be built. A very simple amplifier with differential inputs and differential outputs can look like this: As far as I understand,...
Charly's user avatar
  • 763
1 vote
2 answers
283 views

I have been reading about the voltage gain of JFET, but I am unable to understand how to write the equation for the input side. Can somebody explain the method to write the equation for the input ...
Preet's user avatar
  • 157
0 votes
0 answers
60 views

I need to find a constant current source for a variable LM317 current regulator (schematic below), and I would like to know which JFETs to use. Can somebody let me know how much current I need and ...
Klumpy7's user avatar
  • 402
4 votes
1 answer
150 views

I was solving for poles and zeros of this JFET amplifier with an active load, and found an unexpected zero far off in the response when using the SPICE model. The large-signal and small-signal models ...
Sam Gallagher's user avatar
1 vote
0 answers
150 views

Id is the sum of IB and IR1 with IB small. We can approximatively say Id equals IR1. BJT give an voltage across R1 equals to VBE. VR1 = VBE which is limiting the current flowing across R1. In ...
Acapulco's user avatar
2 votes
1 answer
316 views

I want to derive the input impedance of this JFET circuit : simulate this circuit – Schematic created using CircuitLab What is the method in order to derive the input impedance of this circuit? ...
exolune's user avatar
  • 151
2 votes
2 answers
1k views

Electret mics supposedly use current of 0.5mA to 1.5 mA. In all JFETs the current at VGS = 0V is around 10mA. What JFET is then used in electret mics to be able to be powered by a laptop for example ...
LEXOR AI's user avatar
  • 539
6 votes
2 answers
202 views

I'm working on a device and I'm encountering some problems. Basically the device pushes varying currents through a variable load using a current source and an H-bridge. For safety purposes, the load ...
Jonieboy95's user avatar
6 votes
1 answer
390 views

I have come across this circuit with two JFETs as shown below. Does anyone know what is the purpose of these two JFETs?
user42423's user avatar
  • 365
4 votes
3 answers
2k views

I am in search of a method to implement voltage clamping or overvoltage protection for a sense line operating at 3.3V, with an ultra-low leakage current of ideally less than 1 nA. If achieving less ...
Olgidos's user avatar
  • 175
2 votes
1 answer
180 views

When \$V_\text{DS} = V_\text{P}\$, thus \$I_\text{D}\$ will achieve maximum value hence equal to \$I_\text{DSS}=10\text{mA}\$. By substituting \$I_D\$ into \$I_\text{D}=I_\text{DSS}\left(1-V_\text{GS}/...
Chee Yi Luay's user avatar
1 vote
1 answer
343 views

I've recently purchased a 12v compressor with a control unit attached (QDZH35G - usually meant for refrigerators or A/C units, but this is for a DIY project). The speed of the compressor can be ...
Justin's user avatar
  • 111
2 votes
1 answer
1k views

I followed a guide by FesZ Electronics on biasing a JFET amplifier and came up with the following circuit: simulate this circuit – Schematic created using CircuitLab I then hooked up to a 0.01mA ...
Phönix 64's user avatar
3 votes
2 answers
552 views

I need to protect a op amp of a TIA from too high voltages/currents From its datasheet, the LMP7721 support a maximum differential VIN Differential of –0.3 - 0.3 V. I cant use general diodes, due to ...
Olgidos's user avatar
  • 175
2 votes
1 answer
260 views

All sketches of JFET construction that provide an actual 3D impression suggest that the channel is buried, e.g. here. I imagine that the formation of such a channel geometry requires at least two ...
tobalt's user avatar
  • 25.6k
2 votes
1 answer
217 views

As a sequel of this question, I built a mathematical model for the Id current of the following (same) JFET circuit: For a simplified model, I took LAMBDA=0 and set ...
edwillys's user avatar
3 votes
1 answer
215 views

I'm simulating the following circuit in PySpice: simulate this circuit – Schematic created using CircuitLab In this configuration, the N-JFET is always in saturation mode, as you can see by the ...
edwillys's user avatar

1
2 3 4 5
7