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I am working on the AGC circuit below and was recently made aware of the fact that Vgs(off) varies widely for most JFETs including the JFET I was planning to use in my circuit J113 which has a minimum and maximum Vgs(off) and -0.5V and -3V source. The JFET is one of the critical components of my circuit as I use it as a voltage controlled resistor.

For reference my AGC circuit is below VGA Circuit Using J113 to provide variable resistance

I would like to get a better understanding of how the Drain-Source resistance will vary with Vgs(off) so I have created the circuit below. This circuit consists only of a singular jfet and a variable input DC signal. Note that I am using the .model spice directive to vary the Vgs(off) of the jfet.

Circuit Used to Understand how Vgs(off) impacts Drain-Source Resistance

Once I simulate the circuit I use a python script and PyLTSpice to load the data and calculate the resistance across the jfet as a function of the gate's voltage.

Resistance of JFET vs gate voltage

Using the .model directive I can change Vto (Vgs) of the jfet to whatever value I want. For example if I change Vto to 0.5V I get a plot like the one below for resistance vs gate voltage.

enter image description here

My first question: Is varying Vto an accurate way to model the JFET with differing values of Vgs(off) or are there other parameters which would also change if Vto changes? Per the lt spice model description it looks as though beta and lambda are the only other two parameters likely to impact the resistance of the jfet.

My second question: How can I negate the impacts of variable Vgs(off) in my design? Should I design based on the performance for minimum Vgs(off)? Are there other discrete that could act like a controllable resistor that have lower variability?

Thank You

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  • \$\begingroup\$ I don't understand why you need to use Python. You should be able to do this plotting completely within LTspice itself. Anyway, for more accurate modeling of JFETs, I would consider using QSPICE instead, especially for subthreshold conduction support. \$\endgroup\$ Commented Dec 27, 2024 at 19:23
  • \$\begingroup\$ Also, consider adding a voltage divider. The first resistor (100k) is from the drain to the gate and the second resistor (100k) is from the gate to the "input". web.archive.org/web/20140210131332/http://graffiti.virgin.net/… \$\endgroup\$ Commented Dec 27, 2024 at 19:53
  • \$\begingroup\$ When I 1st designed an AGC for aerospace throat microphones shared by all workers in airsuits in a reactor building, I made rough design specs for squelch level, attack & decay times and reference output levels controlled by a 1mA drop on a rectifier diode, I got consistent results. I see no design specs in your question. Only a problem with a poor design. The peak error voltage from the linear amplifier had a stable reference. Then signal conditioning was applied to achieve the specs were amplified to the active attenuator with enough gain to null the error to the required tolerances. \$\endgroup\$ Commented Dec 27, 2024 at 23:56
  • \$\begingroup\$ The attenuator could be a T-pad with a JFET or NPN to control the inverting input level. My reference was the peak amplitude of the bandpass-filtered audio signal from a 0.6V diode. Your reference is the \$V_{gs(off)}\$ of a JFET which has poor tolerance compared to a 1mA Si diode. If you prefer my solution, I may write up an answer if I have time while you define some specs in the meantime. \$\endgroup\$ Commented Dec 27, 2024 at 23:59
  • \$\begingroup\$ @D.A.S.I would certainly be interested in seeing your design. I am using a USB sound card for this and it doesn't have specs on the minimum input voltage level. Once I get it in the mail I will use a sig-gen to see if I can come up with a approximate squelch level. I'll also do some work to come up with timing requirements, my end application would be very similar to you. I am hoping to interface this with a throat mic for a hobby project. A couple questions on the design you described \$\endgroup\$ Commented Dec 29, 2024 at 2:16

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"How can I negate the impacts of variable Vgs(off) in my design?"

You could add some gain (such as a non-inverting op amp) to drive the FET gate and add a Zener is series with D1 to set the AGC threshold. That would minimize the effect of Vgs variations on the output AC voltage.

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  • \$\begingroup\$ Sure, that would work in theory. But in practice? You get a much jerkier AGC—the kind of sound that grates on your nerves and leaves you feeling irritated and exhausted. \$\endgroup\$ Commented Dec 27, 2024 at 18:17
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Your second question? Now you’re onto something I’d actually explore. There’s a special kind of bipolar transistor designed to be symmetrical around the base. See, most BJTs have a smaller, heavily doped emitter and a bigger, lightly doped collector. But if you make the structure more balanced, you get a transistor that’s much better suited for controlling AF signals without passing any DC to the collector.

One of those would step in nicely for your J1. Just flip the diodes (D1, D2) around and tweak the loop gain for the AGC feedback. Keep in mind, a BJT’s got way more transconductance (gm) than a JFET, so you’ll need to adjust for that.

Since it’s a BJT, the base "thresholds" are tight and don’t vary much—just keep the drive impedance reasonably low. They’ve usually got very low minimum "on-resistance," but fair warning: a tiny fraction of the base drive might sneak onto the signal line.

These are often called “muting transistors,” and Rohm still makes them. Think 2SD2704K, 2SD2654, 2351, 2226, 2114, or even IMX25 (dual) and EMX26 (dual). They’ve also got options with built-in bias resistors, like DTC614, 623, and 643. Toshiba used to make classics like the 2SC2878 and 2SC3326, but those are history now. Progress, I guess.

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Try to extract \$V_{GS(off)_{min}}\$ , \$I_{DSS_{min}}\$ and \$V_{GS(off)_{max}}\$ , \$I_{DSS_{max}}\$ from the datasheet.

And next use \$V_{GS(off)_{min}}\$ and \$V_{GS(off)_{max}}\$ as \$V_{T0_{min}}\$ , \$V_{T0_{max}}\$ in simulation.

And for the beta use this: $$Beta_{min} = \frac{I_{DSS_{min}}}{|V_{GS(off)_{min}}|^2}$$ $$Beta_{max} = \frac{I_{DSS_{max}}}{|V_{GS(off)_{max}}|^2}$$

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  • \$\begingroup\$ I think there's a typo in one of the \$V_{T0}\$'s. Unless I'm misinterpreting something? \$\endgroup\$ Commented Dec 27, 2024 at 19:27
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    \$\begingroup\$ @SteKulov I fix it. Thanks. \$\endgroup\$ Commented Dec 27, 2024 at 19:29
  • \$\begingroup\$ @G36 Thank you for the answer it is very helpful, are there any sources you would recommend for reading further about these equations/relationships? \$\endgroup\$ Commented Dec 28, 2024 at 23:54

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