3
\$\begingroup\$

I'm working on creating a logic circuit that can detect which of the signals B and C have the first rising edge after a falling edge of signal A. The output should be low if B is first and high if C is first. Only the first edge matters. After the first edge, the output should be hold at least until the next falling edge of A. I have to read the output while signal A is high to control my stuff. The pulse widths are 50 to 300 nanoseconds for B and C, and about 5 µs for signal A. Here's what the pulses look like:

A:
______                                        ______________________________
      |______________________________________|                              |__________
      
B:    
                   __         _                   _            __               _    
__________________|  |_______| |_________________| |__________|  |_____________| |______
                                                                               ↓
C:                                                                             ↓
          __             __                     __            _                ↓     _
_________|  |___________|  |___________________|  |__________| |_______________↓____| |_
         ↓                                                                     ↓
Output:  ↓                                                                     ↓
         ↓                                                                     ↓
         ↓_____________________________________________________________________↓
_________|                                                                     |________

Do you have any idea how to do this with flipflops? I've tried some combinations with D-flipflops but it didn't work.

\$\endgroup\$
8
  • \$\begingroup\$ Welcome! Please add what you already tried to the question so we know why/where exactly you're stuck. \$\endgroup\$ Commented Jul 10 at 16:03
  • 2
    \$\begingroup\$ "The output should be low if B is first", but it's already low? Do you want the output to reset to something else (e.g. high-impedance)? \$\endgroup\$ Commented Jul 10 at 16:09
  • 2
    \$\begingroup\$ manxmsnn, Let's assume for a moment that you have attempted the very minimum of thought on this problem. Show us your thinking. Not your work product, exactly. We don't need to see a mess that doesn't work. What we do need to see is how you think about problems like this. Expose your brain. Let us see your brain trying to solve this problem, in concept. How do you approach it? Where does your eye first focus in trying to break this down into parts? The output is far less important to see. \$\endgroup\$ Commented Jul 10 at 16:23
  • \$\begingroup\$ What should happen if B or C or both are high during the fall of A? \$\endgroup\$ Commented Jul 10 at 16:24
  • 2
    \$\begingroup\$ @Andyaka: As the problem is currently stated, nothing at all. Only the rising edges are significant. \$\endgroup\$ Commented Jul 10 at 17:59

5 Answers 5

Reset to default
7
\$\begingroup\$

Dave has provided one possible approach that presents a clear mechanism. But some time has passed and I'd now like to add a different perspective to help expand your thinking. It's my hope that having two views will help you see a third way yet to go -- and one that speaks still better to your own thinking.

With that in mind ...

When A is HI neither B nor C should be observed. When A is LO then if one of B or C transitions HI then C should be latched to the output.

The following may achieve that:

enter image description here

If A is HI then the NOR output will be LO and the two AND gates will block any observation of B or C and the XOR output will be LO and the OUT FF will hold its last value.

If A is LO then the XOR gate will accept a rising edge on either B or C (but not both at the same time) and cause the OUT FF to latch the C state as the desired output value. This edge at the output of the XOR gate also sets the EVENT and thereby blocking any further observation of transitions on B or C.

Be creative. Think for yourself. But use the ideas of others as leverage.

\$\endgroup\$
3
  • \$\begingroup\$ "When A is HI neither B nor C should be observed." Says who? The only requirement stated in the question is that a falling edge on A restarts the detection process. \$\endgroup\$ Commented Jul 11 at 14:03
  • 1
    \$\begingroup\$ Thanks for the input! I've recreated your approach and modified it. This works great and is a bit simpler than @Antonio51 solution. \$\endgroup\$ Commented Jul 11 at 16:37
  • 2
    \$\begingroup\$ @DaveTweed I read it as following from "I have to read the output while signal A is high to control my stuff". And the very fact that you can read the same thing I did and find a differing point of view is why I wrote in my first paragraph, "I'd now like to add a different perspective to help expand your thinking." My motivation inspiring me to bother adding an answer to yours, at all, was precisely because I could see a different interpretation and wanted to express that. \$\endgroup\$ Commented Jul 11 at 22:01
4
\$\begingroup\$

Here's one way of looking at it that may get you started on a solution:

  • If the output is high, the only thing that can flip it low is a falling edge on A followed by a rising edge on B.
  • If the output is low, the only thing that can flip it high is a falling edge on A followed by a rising edge on C.

So you basically need two sequence detectors, only one of which is enabled at any given time by the current state of the output.

Here's my solution. It looks messy because CircuitLab doesn't have an edge-triggered DFF with asynchronous clear, so I needed to draw the internal logic explicitly inside the dashed boxes.

Each DFF is being used as an edge detector. Together, they capture falling edge on A followed by rising edges on B and C. Whichever of the latter occurs first clears or sets the output FF (the two NOR gates on the right) and then resets all of the edge detectors.

If you were going to implement this in SSI/MSI TTL, you'd just need two packages of 74xx74 and one package of 74xx02.

schematic

simulate this circuit – Schematic created using CircuitLab

timing diagram from simulation

\$\endgroup\$
1
  • 1
    \$\begingroup\$ Thank you for your answer. It works great! \$\endgroup\$ Commented Jul 11 at 22:29
2
\$\begingroup\$

It let me search for a "while" ...

Made with microcap v12, no "delays".

enter image description here

enter image description here

\$\endgroup\$
1
  • \$\begingroup\$ Thanks a lot Antonio51! I've modified the circuit a bit. I changed the connection of the last D-FlipFlop (U34) with C → D and QB left open, so the FlipFlop checks if the pulse of q2 "is equal" to C. If it's the case Q goes HI if not Q goes LO. This works very good for my case! \$\endgroup\$ Commented Jul 11 at 13:53
1
\$\begingroup\$

I tweaked @periblepsis's and @Antonio51's methods and included a screenshot of the final circuits from my LTSpice simulation down below. You can also see @DaveTweed's solution in the screenshot. All solutions work great! In LTSpice, @periblepsis approach is the fastest and also the simplest.

Thanks for the help and support!

P.S. I had to use the OR-NOT combo in @DaveTweeds method to get the simulation running.

circuits to detect if signal B or C rises first

\$\endgroup\$
0
\$\begingroup\$

The wanted operation resembles what's happen in a complex flip-flop, so we can perhaps approach the design like flip-flops seem to be constructed internally as non-synchronous state machines. The internal states are stored in simple SR-flip-flops; one flip-flop per a state variable.

The rest of the answer is fully rewritten, because a comment told that the output signal was not held long enough

To keep the state diagram simple we can use multilevel design. A simple state machine triggers an external flip-flop which stores C to be used as the output (=OUT in the circuit drawing) when either C or D jumps from L to H after A has fallen to low. The OP had promised that C and D are never high at the same time.

This is my state diagram:

enter image description here

The state variables X and Y are stored in static NAND flipflops in the next image. They need negative set and reset signals. But that does not make the circuit more complex. The triggering signal "store C" can be the same as which is used to reset variable Y.

enter image description here

The formulas for making the state variable set and reset signals with gates are shown in the next image. They are written at first as positive because that's somehow easier to compare to the state diagram. negative reset Y is made with De Morgan's rule.

enter image description here

The used design method is somehow systematic, but it assumes that all signal delays in gates are consistent. That can be very bad assumption when the circuit is built of diverse parts on a wired hobby breadboard. Using clocked flip-flops is much safer way, because the inputs can have enough time to settle properly.

\$\endgroup\$
4
  • \$\begingroup\$ Where's the required output signal in this design? I think you need at least one more FF. \$\endgroup\$ Commented Jul 12 at 20:08
  • \$\begingroup\$ It's said in text: Combine X and Y with a gate. For example OUT = X'Y. I hope that OP has other circuitry which knows when to check the signal OUT. \$\endgroup\$ Commented Jul 12 at 20:12
  • \$\begingroup\$ But it has been said multiple times that the output must be held across multiple cycles of the A input. This design does not accomplish that. \$\endgroup\$ Commented Jul 12 at 20:13
  • \$\begingroup\$ True. It needs more internal states or an extra memory element which holds the output long enough. \$\endgroup\$ Commented Jul 12 at 20:39

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.