I have a question about digital circuit design. This is the situation. I have a pulse train. The length of the pulse train is not fixed. So the use of a counter is out of the question. I need to drive a signal high at the first rising edge of the pulse train and need to keep it high as long as I wish. And also I must be able to drive it low when I wish. How can I design a digital circuit to do this? Thanks in advance!
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3 Answers
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Consider an Set-Reset Latch (or SR Latch:
Such a latch can be made of NOR (as above) or NAND gates. And is usually found as a complete circuit in many integrated circuit logic families.
In the above example, the Reset and Set lines are normally low. Bringing the S input high forces Q high and Q-Not low. Bringing R input high forces Q-Not high and Q low. Q and Q-Not feed back to the input of the NOR gates to maintain the new state.
You can send your pulse train into the S input and force the Q output high upon the first falling edge. Use an inverter on the pulse train if the first rising edge is desired. Then, momentarily bring the R input high to reset the Q output low.
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\$\begingroup\$ Hey, I just did what you recommended. There is a small issue however. The signal goes high before the first pulse. \$\endgroup\$Programmer Dude– Programmer Dude2018-03-30 14:45:03 +00:00Commented Mar 30, 2018 at 14:45
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\$\begingroup\$ I am a little confused: Either you want to set the latch on the rising edge of the pulse train. But there is an unwanted rising edge before the pulse train of interest that you want to ignore. (If this is the case, keep the Reset input high until you are ready to sample the pulse train.) Or you want to set the latch on the falling edge of the pulse train. (If this is the case, add a NOT gate between the "R" symbol and the input of the NOR gate.) \$\endgroup\$st2000– st20002018-03-30 14:58:12 +00:00Commented Mar 30, 2018 at 14:58
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\$\begingroup\$ st2000, It actually worked. I had a small mistake in my breadboard layout. Many thanks \$\endgroup\$Programmer Dude– Programmer Dude2018-03-30 15:03:47 +00:00Commented Mar 30, 2018 at 15:03
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Look up something called a Set/Reset Flip-Flip. In their pure form, these have two inputs. When the SET input is asserted, the output goes high. When the RESET input is asserted, the output goes low. When neither is asserted, the output retains its state.
S/R flip-flops can be made with two NAND gates, but you can get them ready made in logic chips, like the 74xxx series.
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What is a 1 bit edge sensitive memory cell?
Async State Sensitive :
Two gates with cross feedback form a Latch . This has two inputs Set and Reset, it can be positive or negative logic on input depending on gates if normal or inverting type with NOR, NAND This is now a 1bit register. Your choose the output depend such that Reset overrides Set.
Edge sensitive input , async reset:
But if both are high or Reset during a pulse train level=1, then you use an edge sensitive FF for pulse and R to clear.
