\$V_{CC}\$ and GND are distinct from, and (almost) unrelated to \$V_{IN}\$ and \$V_{OUT}\$. Your "inverter" circuit is representative of a single gate, and each such gate will have its own set of four terminals, but when there are many such elements in a single integrated circuit (IC), \$V_{CC}\$ and GND are shared, as I will explain.

An IC can contain many gates. The 7404 IC and its variants the 74LS04, 74HC04, 74AC04 amongst others, all contain 6 inverters, each having one input pin and one output pin which are independent from the power supply.

A single inverter (or other gate type) will usually be drawn without power supply pins, but really each one does have its own pair of supply terminals. They are almost never drawn on a schematic, it is expected that the reader understand that they are implied. I'll draw them explicitly here:

All the gates in a single IC share the same power supply, via the IC's pins \$V_{CC}\$ and GND, but their inputs and outputs are independent. Each inverter inside the IC will correspond to your own inverter schematic, but they all share the same power supply. If the gates inside the IC were all drawn with explicit supplies, the IC diagram would look like this:

The IC's two supply pins provide energy for all the individual inverters to operate. The 7404 and 74LS04, variants named "TTL" require a potential difference between \$V_{CC}\$ and GND of 5V, or very close. The so-called "CMOS" devices, 74HC04 and 74AC04 can operate with a supply potential difference of anywhere between 2V and 6V. An appropriate power supply would be connected to the IC like this:

I've used a battery to apply a 5V potential difference between the supply pins, but that could be any source of 5V. It's important to understand that engineers use the ground symbol to indicate the node which we deem to have "0V potential":

From now on, when I quote some potential such as "plus-five-volts, or +5V", that value is with respect to my arbitrarily defined "zero-volt point", or "ground", or "GND". Therefore, the positive battery terminal (or other voltage source), which is 5V higher in potential than its negative terminal, will have potential \$0V + 5V = +5V\$, and is labelled as such. Anything connected to the battery negative will have 0V potential.

The supply pins and input/output pins are independent, but not entirely unrelated. Supply pins also define what potentials the gates will interpret as "high", a logical "1", and low, logical "0". The positive supply pin (14, \$V_{CC}\$), determines what potential will represent logic 1, and the negative supply pin (7, GND) defines the potential that will represent logic 0. You have some flexibilty; any input potential close to +5V (say, +4.5V) will be interpreted as "high", and any input potential close to 0V (say, +0.5V) will be interpreted as "low". See the IC's datasheet to learn the exact threshold potentials.

Since all connected nodes have the same potential, if you wish to signal to an inverter that its input is logic 1, you may simply connect that input directly to \$V_{CC}\$, +5V. That may be the source of your confusion, causing you to associate \$V_{CC}\$ with an input or output. The supply pins and the input/output pins are only related in-so-far that the supply pins define logic level potentials, and the others interpret signals based on that information. Similarly, connecting an input directly to GND, 0V, will signal to the inverter that its input is low, logic 0, but that does not mean that the GND pin and an input or output are "the same thing". The potentials may be the same, but supply and signals are otherwise unrelated.

Since an inverter inverts, in the diagram below, pin 10 is at 0V potential, pin 8 is at +5V, and pin 2 has +5V:

It is not wise to assume the potentials of any unconnected pins, since ambiguous inputs produce ambiguous outputs. Nor is it wise to leave any input unconnected, unless the datasheet tells you it's safe to do so. Different ICs behave differently in such circumstances, and it's up to you to read the datasheet and learn about the IC's quirks. In general, TTL ICs will interpret an unconnected input as high, but CMOS ICs make no such promise. Leaving a CMOS input unconnected is likely to cause oscillations, RF emissions, and unnecessary power consumption. You are advised to connect the inputs of every unused gate to either 0V or +5V, to prevent this.

You do not have to provide an input potential by connecting the input directly to one of the supply "rails", 0V or +5V. Any source of potential can be used, perhaps the output from another gate, or a comparator, or switch+resistor combination, anything, really. Just make sure that the source of potential never falls outside the range 0V to +5V, or whatever supply potentials you have employed. For example, applying +7V to the input of a gate powered with 0V and +5V will likely damage it. Applying +2.5V to an input won't cause damage, but that's an ambiguous logic level, and you can't be sure what the gate's output would be, or even should be.

If your schematics had to include every detail of the circuit, as mine above have, they can quickly become very cluttered. Usually, therefore, only the critical details are included, the rest is implied. My last schematic above could be drawn like this:

^{simulate this circuit – Schematic created using CircuitLab}

An engineer reading that could infer some pertinent information that isn't shown explicitly. For example, the inputs to gates are 0V and +5V, implying that the gates' supplies are 0V and +5V also. The pin numbers are also shown, and from that it can be assumed that this is an IC, the name of which will surely be found elsewhere in the schematic or documentation.

Just to drive home the idea that \$V_{CC}\$ & GND are distinct from inputs & outputs, related only in the sense that they define what is "high" and what is "low", consider this circuit:

^{simulate this circuit}

Here we have three separate ICs, powered by three separate voltage sources. Their grounds are all connected together, so that each IC (and all the gates within it) has the same idea of what "zero volts" is, but they are otherwise all independent.

Still, they will work just fine. The NAND gate IC (74'00) produces its own output potential from its own supply, but it does not care which power supply is used to source the potentials at its inputs. All it cares about is input potential, not the source of that potential. That source can be its own \$V_{CC}\$ or GND, or literally anything else, anywhere else.

Since any output here can be +5V or 0V, it is also incorrect to directly equate \$V_{CC}\$ or GND nodes with an output, although internally a gate will use either its own \$V_{CC}\$ or its own GND to derive its own output potential. They are related, but they are not the same thing.

No they are not the same thing.

Vin equals the data input A on the other diagram.

VCC equals the power supply in order to make the gate function. The other diagram assumes only the logic function is important, not the fact that all logic gates require a power supply, as they don't work without.

Are Vcc and Vin the same thing for logic gates?

No. You are conflating signal ins and outs with power ins and outs. They are not the same.

Also, many (most?) schematic drawing programs allow you to hide nets such as Vcc / Vdd / Vee / Vss / GND / whatever. The connections are maintained in the program files and included in exported files such as photoplotter and drill files. Not showing them removes a lot of unnecessary clutter, especially in logic diagrams. This has been going on for so many decades that it rarely is explained, and can be confusing.

Beyond verbal clichés

OP's question touches upon fundamental concepts in electronic circuits that have become so ingrained in our minds that we use them almost mechanically as verbal clichés. And when we are asked such a direct question, we begin to wonder how to answer. So, in the end, we arrive at the idea of abandoning high-level explanations and descending to the lowest possible level.

Picking an exemplary circuit

Using TTL a NOT Gate could be built like this...

This TTL circuit is not the best example to illustrate your question because it is unnecessarily complex. Instead, I suggest building a simple NOT logic gate (conceptual, NMOS, BJT...) step by step, revealing the role of voltages at each stage (we will give the voltages descriptive names to aid in our understanding). After that, if you would like, we can examine your TTL circuit in the same step-by-step manner.

Building a simple NOT gate

Since these are conceptual diagrams, I have used, when possible, convenient decimal values for the voltages and resistances.

Perfect input voltage source

The most basic electrical circuit contains two elements - a voltage source and a load. With the help of electric current, in power engineering and high-current electronics, they transmit energy. In low-current digital electronics, we transmit data through voltage (here 0 V represents "0" and 10 V represents "1"), and Vin is typically referred to as the input voltage to the load.

^{simulate this circuit – Schematic created using CircuitLab}

If the voltage source is "ideal" (with zero internal resistance), then its entire voltage of 10 V is applied to the load.

Visualized load

To visualize the current through load without cluttering the schematic, I have replaced the load resistor RL with an ammeter having the same internal resistance of 10 kΩ. In other cases below, I have replaced a resistor with a voltmeter having the same resistance (see more in Can we combine meters with resistors?). Here, a voltmeter is not necessary because the voltage source is "ideal" and it completely determines the voltage.

^{simulate this circuit}

Imperfect input voltage source

However, if the input voltage source is poor and has some internal resistance Ri = 1 kΩ, a voltage drop of about 1 V occurs across it. The voltage across the load (VL = 10 V) decreases by that amount (here, I have swapped the meters - the ammeter represents Ri and the voltmeter represents RL).

^{simulate this circuit}

Moreover, we want the voltage across the load to be inverse to the input voltage.

Adding supply voltage

These problems led to the ingenious idea (central in electronics) of not controlling the load directly by the input voltage but by another powerful supply voltage Vs controlled by the input voltage. Controlling Vs is achieved through "active" elements, which are essentially voltage-controlled resistors. They are non-linear but this is not particularly important for revealing the overall idea. So, we can simulate them by an ordinary variable resistor Rvar (rheostat) having two resistance values - very low (e.g., 10 Ω) and very high (e.g., 1 GΩ). The "input voltage" will be us moving the slider of the variable resistor.

"Floating" load

Vin = 0 V ("0"): So, let's connect Rvar in series to (under) RL and first increase its resistance to 1 GΩ...

^{simulate this circuit}

Vin = 10 V ("1"): ... then decrease Rvar to 10 Ω.

^{simulate this circuit}

So, the pair of resistors creates a voltage divider, producing an output voltage that varies from near 0 to Vs. Note, however, that the load is connected with one of its terminals to the positive terminal of Vs, and not to its negative terminal (the so-called "ground") as is customary. This creates problems because the load may represent the same stage whose input is grounded. As a result, Rvar will be short circuited.

Grounded load

It is easy to guess that we can solve the problem with a simple "complementation" trick by taking as an output not the voltage across the load but its complement to Vs. To implement this idea, we replace the load with a constant resistor R and connect the load in parallel to Rvar.

When Vin is low ("0"), Rvar is high. The load is connected through R to Vs and its voltage is high ("1").

^{simulate this circuit}

Now, when Vin is high ("1"), Rvar is low. The load is shunted and its voltage is low ("0").

^{simulate this circuit}

Voltage divider viewpoint: Actually, the two resistors R and Rvar form a voltage divider with a voltage-controlled "gain" G = Rvar/(Rvar + R).

Why inverting? Since Rvar decreases when Vin increases, G, accordingly Vout, also decreases; so the circuit is inverting. This is how we have created NOT gate.

NMOS implementation

To make a real gate, we can replace the voltage-controlled resistor with an NMOS transistor.

Vin < Vth: When the input voltage is lower than its threshold voltage Vth, the transistor is cut off. The output (drain) voltage is close to Vdd.

^{simulate this circuit}

Vin > Vth: When the input voltage is higher than the threshold voltage, the transistor is conducting. The output (drain) voltage is close to zero.

^{simulate this circuit}

By the CircuitLab DC Sweep Simulation we can plot the graph of the output voltage when vary the input voltage from 0 V to 10 V.

As you can see, the transistor is an analog device but we have made it act as a digital one. It is an analog device only in a very narrow region of its characteristic (around Vth); in the remaining region, it is a digital device.

BJT implementation

We can also replace Rvar with a BJT. We only need to add a base resistor Rb due to the specificity of its input (PN junction).

^{simulate this circuit}

^{simulate this circuit}

The threshold voltage of the BJT's gate is lower (about 1 V).

Disadvantages

The simple NOT gate above works well when the transistor is on (Vin is high). The load is reliably shunted by the low resistance of the transistor and the output voltage is almost zero. Then it is good for the upper transistor to have a high resistance.

However, when the transistor is off (Vin is low), the upper resistor R (relatively high-resistance) is connected in series with the load and forms another divider with it. Almost 1 V is lost on R and 9 V remains on the load. Then it is good for the upper transistor to have a low resistance.

Obviously, there is a contradiction - on the one hand, we want R to be high, but on the other hand, we want it to be low. So, the problem is that R is "static" with the same 1 k resistance in both states of the logic gate.

Complementary NOT gate

The solution is obvious - we replace R with another variable resistor Rvar2 that changes its resistance opposite to Rvar1, complementing it.

^{simulate this circuit}

^{simulate this circuit}

CMOS implementation

To implement this brilliant idea with a MOSFET, we simply replace R with the complementary PMOS transistor Mp and control it with the same input voltage.

Vin < Vth: When the input voltage is lower than the threshold voltage, Mn is off and Mp is on. The output (drain) voltage is close to Vdd.

^{simulate this circuit}

Vin > Vth: When the input voltage is higher than the threshold voltage, Mn is on and Mp is off. The output (drain) voltage is close to zero.

^{simulate this circuit}

The result is obvious - a steep transition from one state to another reaching the power supply rails.

Conclusions

• In a NOT logic gate, two voltages are input: one, called the "input" voltage, controls the other, called the "supply" voltage. As a result, an "output" voltage is produced, which is a portion of the supply voltage.

• The three voltages are referenced to a common circuit terminal called "ground" that is connected to the negative terminal of the supply voltage.

• This configuration is inverting (NOT gate) because Rvar decreases when Vin increases. As a result, RL is shunted and Vout decreases.

• The problem of the simple NOT gate is that R is a "static" resistor with the same resistance in both states of the logic gate.

• The remedy is to make R variable in the opposite direction by implementing it with a PMOS transistor. Thus the CMOS NOT gate is obtained.