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I am trying to generate two clocks of X-MHz each, X being a value ranging from 5 to 100. I chose si5351 chip for this as a breakout board was easily available from Adafruit. I used attached code to generate clocks from CLK0 and CLK1 outputs with same frequency but 90 degree phase difference.

main.c

void init()
{
const int32_t correction = 978;

si5351_Init(correction);
si5351_SetupCLK0(5000000, SI5351_DRIVE_STRENGTH_4MA);
si5351_SetupCLK1(5000000, SI5351_DRIVE_STRENGTH_4MA);
si5351_EnableOutputs((1<<0) | (1<<1));
}


// main is called after all the nrf52832 startup code is executed
int main( void )
{

init();
return 0;
}

si5351 I2C driver I used was from github I2C Driver.

I added following code in the si5351.c file to generate CLK1 output at 90 degree offset.

void si5351_SetupCLK1(int32_t Fclk, si5351DriveStrength_t driveStrength) {
si5351PLLConfig_t pll_conf;
si5351OutputConfig_t out_conf;

si5351_Calc(Fclk, &pll_conf, &out_conf);
si5351_SetupPLL(SI5351_PLL_A, &pll_conf);
si5351_SetupOutput(1, SI5351_PLL_A, driveStrength, &out_conf, 50);
}

I am using nrf52832 dev board to drive I2C over which the si5351 breakout board is connected. nrf52832 board also powers the si5351 breakout board. Now when I measure the outputs on oscilloscope every time I restart the system, phase offset between two clocks is always different. I have no idea why si5351 generates clocks with different phase each time I power on the whole system, while the code on nrf52832 is same.

Attached are the snapshots taken after a reset of the system where the phase applied on two clocks was 90 degree. enter image description here enter image description here enter image description here

Can anyone point me if si5351 has reliability issues or I am doing any steps wrong here. Please note that correction value for si5351 is taken as it is from github code.

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  • \$\begingroup\$ A quote from a Si5351 guru Hans Summers: If you don't do a PLL reset under these two circumstances then the phase offset will be random. These two conditions are:(1) A change to Multisynth divider registers (as distinct from PLL feedback divider); (2) whenever you switch outputs on/off using Clock_Control_registers like register 16 The original SiLabs documentation is a bit sketchy, and is misleading in places. We should not be too upset - documenting the dependencies of nearly 200 registers is daunting. \$\endgroup\$ Commented Jul 4, 2023 at 18:18
  • \$\begingroup\$ FIY see also this discussion eg: "Two Si5351A outputs CAN be configured with 90-degree phase offset down to 3.2MHz" so perhaps the available phase offset register is too small at your lowest frequencies? \$\endgroup\$ Commented Sep 18, 2023 at 20:07

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