Measuring the compensating loop gain \$T\$ on a final prototype is essential to check the robustness of the compensation strategy. By compensation strategy, I imply the poles and the zeroes, placed to force a given crossover \$f_c\$ with adequate phase and gain margins. Once the theoretical analysis has been done - using equations or with an averaged model - the measurement on the prototype will tell if your model matches the real board. If not, then you need to feed it back with properly-characterized components.
The keyword here is margin: how much margin does your compensated loop gain have, before it becomes unstable? You know that the output capacitor ESR will move with temperature, age and production spread. Same with the optocoupler CTR and pole and so on. How will your converter react when these are varying along the power supply lifetime? If you don't have an idea of the margin you have, you can't be sure you have a solid design. And the only way to obtain an answer is by measuring the small-signal response of the loop via a frequency-response analyzer or FRA (see my answer on SE here).
The small-signal transient response of a converter depends on its output impedance \$Z_{out}\$. This output impedance is linked to the loop gain by \$Z_{out}(s)=\frac{Z_{out,OL}}{1+T(s)}\$ in which \$Z_{out,OL}\$ designates the open-loop output impedance (without the loop closed). You can therefore intuitively see that the transient response is intimately linked to the loop gain and how you have shaped its response. Without entering into the details, crossover frequency will give you how much undershoot is linked to the output capacitance while phase margin will affect the recovery time of the converter in a transient step.
As I said in the comments section, transient steps are important parts of the validation process, but they come second to loop measurements.
