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Suppose I have 3 separate square-wave digital 5V clocks, named A, B and C. All 3 clocks are running at the same frequency of 1 kHz, and at different phase offsets. Suppose the clock generators that are creating these clock signals can be disabled and restarted arbitrarily, but they cannot be "paused". For the purposes of this example, we can assume all the clock generators are ideal, and that no drifting is present.

Suppose I want to shift the phase offset of clock C by the phase difference between clocks A and B.

For example; If clocks A, B and C have phase offsets of 0°, 20° and 50° respectively, I would seek to shift the phase of clock C by -20° (from 50° to 30°).

This task would be simple to accomplish if the clock generators in my case were some sort of analog circuits which use isolatable capacitors to perform the clock timing, such as a 555 timer. In that case the clocks could have their phase offsets effectively shifted by any arbitrary amount if we momentarily pause the charging & discharging cycles of the timing capacitors by isolating them.

However, in my specific example, the clock generators are digital circuits, and therefore this "pausing" concept is not possible. I was therefore curious whether it is possible to achieve this phase-shifting using only digital logic.

I'm assuming the first step towards achieving this would be to quantify the exact phase difference between clocks A and B. I'm assuming this would be done by using an XOR gate between clocks A and B, which would yield the phase difference between them. However, I'm unsure of how to proceed next.

Since all the clocks are running concurrently at different phase offsets, it proves challenging to achieve this. However, I was wondering whether it would be possible to do this if my clock generators can be disabled & restarted arbitrarily, and whether it would be possible to maybe output the shifted version of clock C as a new fourth clock signal from another clock generator after some digital processing.

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In my specific case the clocks are being supplied from several microcontrollers, each running on their own respective clocks. While it may be possible to pause the firmware running on the MCUs in question in order to achieve the phase shifting of the clocks they're running, I'm worried that using the firmware on the digital MCUs to shift the phases of these clocks would introduce inherent errors into the system, since I'm seeking to shift the phases of these clocks by a continous, not a discrete amount.

However, I'm pretty sure this type of clock synchronization is a linear operation, and therefore this might be possible to achieve using only digital logic. As stated though, whatever logic is required to make this work, it would probably involve starting new clocks in the continous time space.

Is it possible to shift the phase offset of a digital clock by the exact phase difference two separate digital clocks using only digital logic? Are there existing digital circuits made for this purpose?

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    \$\begingroup\$ You need to be a lot more clear about how the clocks are being generated "digitally". And exactly how is "paused" distinct from "disabled and restarted"? If they're being divided down from a common higher-speed clock, the phase can be adjusted easily. \$\endgroup\$ Commented Jun 16 at 14:58
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    \$\begingroup\$ Surely whatever firmware is running on the MCUs can be paused -- perhaps by pausing the clock that the MCU itself is using. This is starting to sound like an XY problem -- perhaps you should describe your overall application. Are you trying to synchronize some digital time-of-day displays? \$\endgroup\$ Commented Jun 16 at 15:04
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    \$\begingroup\$ Are you saying each MCU has its own crystal? With a best-case commercial part you'd get a +/-10ppm clock or 1 in 10000, so for example a 10 MHz clock can actually be 100 Hz adrift i.e. could be 9,999,900 Hz to 10,000,100 Hz. And it will vary with temperature. So the divided-down outputs will drift across each other. \$\endgroup\$ Commented Jun 17 at 7:55
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    \$\begingroup\$ Please add all of this additional information to your question by editing it. Visitors are not supposed to read all comments, and comments can vanish. \$\endgroup\$ Commented Jun 17 at 10:16
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    \$\begingroup\$ (a) Please don't modify your question title or substantially change it once answers have been posted. Those answers may no longer make sense and may receive up/down votes for them in their new light against the question. You can add changes at the question end, marked clearly as new additions. Don't start a new question. (b) What would be useful is to add what you are trying to do and why: what the application is. That's not been done so far and if you're chasing a whim that doesn't really exist or isn't possible, it isn't going to get found out if the overall objective is hidden. Thanks. \$\endgroup\$ Commented Jun 18 at 10:09

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You can do this straightforwardly using a digital logic circuit in a CPLD or an FPGA, which I'll refer to as the Programmable Logic Device (PLD).

The output result waveform R will have the phase difference of B and C as measured on the previous cycle. An R with the phase difference of phB-phC for the current cycle is impossible as, in your example, R's rising edge would start before Cs rising edge - when the phase difference is not yet known.

Using a 10 MHz logic clock for your 1 kHz waveform gives phase adjustment steps of 1/10000th of a waveform cycle or 0.036 degrees. The input metastability filters for A, B and C will cause a phase lag of several clocks (I'd have filters with 3..4 clocks) which can be subtracted from the R generation counters to remove the error. This correction is shown here as constant 4.

For measurement:

  • On A rising edge, clear a 10 MHz-clocked 14-bit counter phaseCtr; otherwise increment phaseCtr every clock.
  • On B rising edge, latch 'phaseCtr' into phaseB.
  • On C rising edge, latch 'phaseCtr' into phaseC.
  • Resultant phase difference is phaseC - phaseB.

For waveform generation:

  • On A rising edge, latch phaseC - phaseB - 4 into phaseRCtr and phaseDiff.
  • On A falling edge, latch phaseDiff into phaseRCtr.
  • On A rising and falling edge, latch new A level into DFF newA.
  • While 'phaseRCtr' is non-zero, decrement it every clock.
  • While 'phaseRCtr' is non-zero, output not newA on R; otherwise newA on R.

I've kept the above simple to keep the principles clear. As such, this circuit has some limits that would be dealt with in a real VHDL/Verilog version. For instance, it requires C to always lag B but coping with B lagging C is easy: always subtract the smaller of (phaseB,phaseC) from the larger of (phaseB,phaseC). But it shows the idea.

A cheap sub-£2 CPLD/FPGA and an (e.g.) 10 MHz clock oscillator will do this. As shown, with input filters, it needs about 86 DFFs plus some more so a 144-register device or more will be great. The manufacturer's free development software will handle such a part, including a simulator so you can see all your waveforms and logic values while you develop and debug.

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    \$\begingroup\$ Thank you for your very detailed answer. Just to make sure I fully understand your approach here, by doing this on an FPGA, you are essentially simulating this entire scenario in a discrete time-space, correct? I see you're using a 10 MHz counter to "save" the initial phase difference. What I was kinda looking for here is an answer in the continous time space, which is where most of the difficulty of this problem lies in. Regardless, your answer's still solid. I will start a bounty on this question tomorrow, and if noone provides an answer in the continous time-space I'll award you the bounty. \$\endgroup\$ Commented Jun 17 at 20:58
  • \$\begingroup\$ @Runsva, in every 1ms period of the 1kHz wave, this circuit will (a) output a result wave based on measurements made in the previous 1ms period, and simultaneously (b) make phase difference measurements for generating the next wave 1ms later. The answer says why it's impossible to generate the waveform in your example in the same 1ms period that the measured waveforms are arriving, so there has to be a 1 waveform cycle lag. I think you're imagining there's a digital yet linear solution, like a PLL's XOR-error feedback circuit. Anyway, thanks for your thanks and let's see where it goes. \$\endgroup\$ Commented Jun 17 at 21:43

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