I have 2 clock banks that will need to be distributed to 64 connections.
FPGA Clock Bank -> termination resistors -> 1-to-4 buffer -> termination resistors -> 1-to-8 buffer
2 x 4 x 8 = 64
The 1-to-8 buffer is actually just a 8 channel buffer I have used successfully in previous designs.
My question is what is the preferred method of routing a clock signal from one trace to 8 traces?
Should I consider routing to one pin, then one trace that connects them all, or a fanout plane?
How much of an effect does impedance or reflections have on each method?
