The memory access latency for the Intel Core i7-11800H (source: chipsandcheese, cpu latency for Intel Core i7-11800H), using DDR4-3200, reveals specific timings: 1 ns for L1, 3 ns for L2, and 13 ns for L3 caches. When considering an open page, the CL (CAS latency) for DDR4-3200 is 15 ns. The cumulative latency till L3 is about 17 ns (1+3+13) and the open row access Tcl is 15 ns, but the overall memory latency depicted on the graph is approximately 110 ns. To account for this disparity, it's essential to factor in memory controller elements such as queue latency, scheduling, and bus latency. Could someone elucidate the breakdown of this 100+ ns of latency? Is there any aspect overlooked in this system analysis?
