I have a question about data transport between two chips with series format.
I have two chips. Chip 1 will sent 8-bits data to chip 2. The picture shows a solution. I will provide a 100MHz clock from a frequency divider for the digital component and a 800MHz clock for the shift register.
One of the problems for this solution is that I will have 2 different phases.
Why will there be two different phases if my div1 and div2 are the same?
Dividers are essentially counters, incrementing on each rising or falling edge (not both). Even a divide-by-two counts from 0 to 1 and rolls over. Unless you have a mechanism to ensure that each one starts counting on the exact same edge (or when others are rolling over to zero), they may have different counts. You can use a reset line, but you'd have to ensure that the reset propagates identically to each counter (including IC operational differences) and takes effect during the same cycle (don't want async reset to occur too near a counting edge, or sync reset to violate setup and hold times).
If you don't synchronize them reliably, they have a good chance of coming up with different counts when they start. Once started, transient noise on the clock could set them out of sync without possibility for correction unless enforced by a separate system.
There is no indication about anything that would make the divided clocks of the chips aligned. Typical solution is to use the actual bit clock or use some kind of data framing to make the chip clocks aligned to each other.
