How To extend bits in a VHDL code

Question

I'm trying to do the following let's say bit extension in a generic way.

First Considering B signal with an even number of bits (NBITS). here is an example:

B = 10100011

Second, adding a zero bit to LSB

B1 = 101000110

Finally, By doing an extension I mean repeating even indexed bits (Bold ones) except for the LSB (0) and MSB ones as:

V= 101 100 001 110

I tried this but it's not working:

process(B1)  
variable j: integer :=0;
begin
  for I in 0 to (NBITS-2) loop
    if (I mod 2)=0 then
      j:=j+3;
      S(j-1 downto j-3) <= B1(I+2 downto I);
   end if; 
end loop;
end process;

I appreciate any help...

EDIT:

Consider NBITS=8 as the given example, I get this error during simulation, While clearly i'm not reaching to 14 for varaible j!

# ** Fatal: (vsim-3734) Index value 14 is out of range 11 downto 0.
#    Time: 0 ps  Iteration: 1  Process: /tb_booth_encoder/t1/line__37 File: /home/ms20.58/LAB02/P4ADDER/vhdlsim/BOOTH_ENCODER.vhd
# Fatal error in ForLoop loop at /home/ms20.58/LAB02/P4ADDER/vhdlsim/BOOTH_ENCODER.vhd line 43
#

EDIT

Here is the full code:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
---------
entity BOOTH_ENCODER is
    generic (NBITS :integer := 8
        );

    Port (    
        B:        In        std_logic_vector(NBITS-1 downto 0) ;
        S:        Out        std_logic_vector((3*(NBITS/2)-1) downto 0));
end BOOTH_ENCODER;

---------
architecture BOOTH_ENCODER_BEHAVIORAL of BOOTH_ENCODER is

signal B1: std_logic_vector(NBITS downto 0);  --Input with extra 0 at LSB

begin

B1 <= B & '0'; --Extension of bit for encoding

process(B1)    
variable j: integer :=0;
begin
    for I in 0 to (NBITS-2) loop
        if (I mod 2)=0 then
            j:=j+3;
            S(j-1 downto j-3) <= B1(I+2 downto I);
        end if; 
    end loop;
end process;

end BOOTH_ENCODER_BEHAVIORAL;
```

"but it's not working:" is not a useful error description. What goes wrong? Syntax error, unexpected result? — Oldfart
– Oldfart, Commented Apr 7, 2020 at 15:10
Well referring to 7th line of the code, it says: # ** Fatal: (vsim-3734) Index value 20 is out of range 17 downto 0. # Time: 0 ps Iteration: 1 Process: /tb_booth_encoder/t1/line__37 File: /home/ms20.58/LAB02/P4ADDER/vhdlsim/BOOTH_ENCODER.vhd # Fatal error in ForLoop loop at /home/ms20.58/LAB02/P4ADDER/vhdlsim/BOOTH_ENCODER.vhd line 43 — Mohammadmahdi Mohammadi
– Mohammadmahdi Mohammadi, Commented Apr 7, 2020 at 15:23
When the input is in 12 bits, the output range is 17 down to 0, But this error does not make any sense to me. since I'm not going to 20! I start by 3 and after 6 iterations reach to 18. — Mohammadmahdi Mohammadi
– Mohammadmahdi Mohammadi, Commented Apr 7, 2020 at 15:28
I cannot see anything with range (11 downto 0) in the posted code, neither will it compile as it is. Please post a complete, compilable reproducer for the problem. — user16324
– user16324, Commented Apr 7, 2020 at 15:57

Mohammadmahdi Mohammadi · Accepted Answer · 2020-04-07 18:39:05Z

I solved the problem by defining an array. my problem was not being able to use "I" iteration for mapping output, I defined an array and use iteration number to point to the proper row. here is the solution:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use WORK.constants.all;

package V_sig_p is
constant NBITS: integer :=8; 
type V_sig is array(0 to (NBITS/2)-1) of std_logic_vector (2 downto 0);
end package V_sig_p;



LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use WORK.constants.all;
use work.V_sig_p.all;


----------------
---- ENTITY ----
----------------
entity BOOTH_ENCODER_a is
    generic (NBITS :integer := 8
        );
    Port (    
        B:        In        std_logic_vector(NBITS-1 downto 0) ;
        S:        Out        V_sig);
end BOOTH_ENCODER_a;


----------------------
---- ARCHITECTURE ----
----------------------
architecture BOOTH_ENCODER_BEHAVIORAL2 of BOOTH_ENCODER_a is

signal B1: std_logic_vector(NBITS downto 0);          --Input with extra 0 at LSB

component BOOTH_ENCODER_comp is
    Port (    
        B:        In        std_logic_vector(2 downto 0);
        V:        Out        std_logic_vector(2 downto 0));
end component BOOTH_ENCODER_comp;

begin

B1 <= B & '0'; --Extension of bit for encoding

GEN_ENC : for I in 0 to (NBITS-2) generate
    GEN_ENC0: if (I mod 2 )=0 generate
        ENC : BOOTH_ENCODER_comp
        port map
           (B1(I+2 downto I), S(I/2));
    end generate  GEN_ENC0;
end generate  GEN_ENC;


end BOOTH_ENCODER_BEHAVIORAL2; 
```

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