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Will a memory mapped i/o operation (in intel processor) still be cached if the address range of the mapped i/o is being typed as write back (WB) even if I use the in/out instruction?

EDIT: This question is solved. I found out that MMIO is cacheable, and MMIO operation can be reordered depending on it's memory type. That's why intel recommended to set MMIO using the MTRR as UC (uncacheable).. I found it on intel software developer manual v3A, which might also be applied on amd processors...

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    Memory mapping with the in and out instructions - how are they related? Commented Feb 10, 2011 at 6:43
  • Memory-mapped I/O uses the same address bus to address both memory and I/O devices. Commented Feb 17, 2011 at 3:51
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    And in/out instructions use a separate address space from system memory. Using in/out is not mmio. Commented May 18, 2011 at 21:54
  • Is the answer based only on the vague recommendation to set MMIO ranges as UC? It hardly seems to prove anything about CPU behavior, maybe it's just to avoid confusing the OS? Commented May 9, 2015 at 8:41

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I'm not aware that MMIO (on x86 systems) can actually be set to be cacheable, but even if they can, I would think using IO instructions would bypass that part of the MMU.The CPU wouldn't be aware that the IO address that you are writing to is internally mapped to the same MMIO address on your device. How are you setting the cacheability of that MMIO region?

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Some devices IO are mapped on some region on physical memory, by setting the MTRR (memory type range registers) you can give control of the cacheability of the memory region..
Sorry for the late reply, and I'm glad you found an answer! Guess I was wrong about the cacheability of MMIO... it looks like it is even common to set prefetchable MMIO spaces as cacheable!

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