ultraembedded / biriscv Sponsor Star 1.1k Code Issues Pull requests 32-bit Superscalar RISC-V CPU linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors Updated Sep 18, 2021 Verilog
sdasgup3 / parallel-processor-design Star 21 Code Issues Pull requests Super scalar Processor design processor-architecture bison flex processor assembler parallel-computing verilog forwarding bypassing pipeline-processor superscalar opcode verilog-hdl instruction-set-architecture instruction-set processor-simulator branch-prediction pipeline-cpu mnemonics instruction-level-parallelism Updated Sep 7, 2014 Verilog
liuly0322 / riscv32-ustc-codh-lab6 Star 1 Code Issues Pull requests USTC 2022 春季学期 CODH 课程综合实验 cpu pipeline vga risc-v branch-prediction rv32i Updated May 25, 2022 Verilog
DoniaGameel / Pipelined-Processor-using-verilog Star 0 Code Issues Pull requests Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor assembler hazard-detection alu branch-prediction control-unit pipelined-processors full-forwarding Updated Jan 29, 2023 Verilog
SaifoSaeed / 5-Stage-RISC-V-Processor Star 0 Code Issues Pull requests Simple 5-stage RISC-V CPU designed with 2-bit branch prediction and a dual-cache system submitted as part of the Computer Architecture course. cpu cache computer-architecture risc-v branch-prediction Updated Jun 30, 2025 Verilog