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I was asked to design a digital system that receives an 8-bit binary input and outputs the binary position of the third '1' bit from the right (LSB side).
The output should be a 3-bit binary number representing the index (starting from 0 for the rightmost bit).
For example:
Input: 10110011
The '1' bits are at positions 0, 1, 4, and 7 (counting from right to left)
The third '1' from the right is at position 4
Therefore, the output should be: 100 (which is 4 in binary)

If there are fewer than 3 bits set to 1, the output can be zero.

My idea is to design two counters:

The first counter increments every time a '1' bit is detected, starting from the LSB and moving toward the MSB. Once it reaches a count of 3, it activates a signal indicating that the third '1' was found.

The second counter simply increments on each bit position as we scan from LSB to MSB. This counter keeps track of the current bit index.

At the moment when the first counter reaches 3, the value of the second counter (i.e., the current position) is saved as the output. If the third '1' is never found, the output should be 0.

I plan to implement this using basic logic components (e.g., counters and a MUX). The first counter’s “reached 3” signal will serve as the select input to a MUX. The MUX will choose between:
the current value of the position counter (if the third '1' was found), or a default value (e.g., 0) if it was not.

I'm struggling with the first part of the counter. I know how to build a circuit that counts the number of 1s in an 8-bit input — it can be done using Full Adders and Half Adders. The problem is how to make it stop once it reaches three 1s, and then output a 1 at that exact moment or output 0 if it didn’t reach that count.

Regarding comments asking for the 8bit counter:

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    \$\begingroup\$ Nice task. How would you establish the binary encoding of the first set bit from the right? The 2nd? (I'd avoid sequential logic here.) \$\endgroup\$ Commented Sep 25 at 8:10
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    \$\begingroup\$ Now that I think about it both counters must be sequential. one counter counts the number of ones and stops at three. the other counter tracks the current bit index from LSB to MSB when the first counter reaches three, the second counter outputs the index if there are fewer than three ones, output is zero. my first 8bit counter is bad then. \$\endgroup\$ Commented Sep 25 at 8:27
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    \$\begingroup\$ When you have put down (!) an idea for 1st bit set, read up on priority encoders. \$\endgroup\$ Commented Sep 25 at 9:07
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    \$\begingroup\$ @Fourier_Asker You say that 000 is okay if there aren't 3 bits set to 1. Since you cannot ever output a binary 0 or 1 for a valid case, would either 000 or 001 be okay? The reason I ask is that both a 000 and a 001 output would be obviously describing the case where there's no answer. That allowance may help with the combinational parts of things. Just asking. \$\endgroup\$ Commented Sep 25 at 11:20
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    \$\begingroup\$ What computer tools do you have available to you and/or allowed to use? There are only 256 possible inputs, you could brute force it with a truth table. Then synthesis tools will optimize it. \$\endgroup\$ Commented Sep 25 at 12:14

8 Answers 8

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Here's two implementations to consider. One comes from both your own and TonyM's consideration about using priority encoders. The other is from a sequential approach using an adder. Both work well in simulation.

(However, keep in mind that digital simulators aren't exactly the same as actual logic. Sometimes, the tricks needed for a simulator aren't the same tricks one uses when building something from parts.)

The upper diagram is combinatorial/combinational. The lower diagram is sequential. The adder in the lower diagram is a simplified adder accepting its own latched output as its input, along with the masked bit to add if present.

(In the upper diagram case, note that the bits are provided to the priority encoders in reverse order. Note, these are example cases with some testing applied. Not polished work. Ask questions and I'll try to make some better sense.)

enter image description here

(Image produced using Neemann's DIGITAL program.)

The only complicated bit for the sequential schematic is the section that develops the clocking for the counter. The clocking for the adder is straight-forward. Keep in mind that this is set up for a simulator to function well. So if this were to be built with real ICs and parts, the behavioral schematic may require some changes. But the basic idea would remain. (Don't let that fact deter you. Details matter, of course. Particularly in a system that depends both on rising and falling clock edges. But that is reality. Using both edges of a clock is a thing worth learning about.)

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    \$\begingroup\$ Wow, very much appreciated. Tried to understand now but due to tireness, I can't really understand now. I will go to sleep now and wake up tommorow and try to understand it better. But this is the more intuitively one I saw here, Thanks!! But just a quick question, what adder is there? I tried to understand and couldn't really see any adder here \$\endgroup\$ Commented Sep 25 at 20:49
  • \$\begingroup\$ Why and "valid" outputs? \$\endgroup\$ Commented Sep 26 at 7:19
  • \$\begingroup\$ @greybeard Can you elaborate a little? Is that just a reference to an earlier comment I made elsewhere about 000 and 001? Or something else? I'm off to sleep so I may be late in addressing further comments... \$\endgroup\$ Commented Sep 26 at 8:14
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    \$\begingroup\$ A third bit set implies a second and first bit had been set: I think the and should always equal the third valid. (See TonyM.'s answer, too.) \$\endgroup\$ Commented Sep 26 at 11:00
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    \$\begingroup\$ Keeping in mind the OP is a student and the intent of the question (as it was posed to them) was to provoke thought and problem-solving, this answer is probably best. It demonstrates combinatorial and sequential solutions using basic building blocks, which is where they are currently at in terms of their studies. It does give them the proverbial fish, but hey we've all been there - as long as something is learned. \$\endgroup\$ Commented Sep 27 at 15:23
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I know this is the brute force solution, but if you are just looking for a chip that can do the job. A regular parallel 8-bit parallel ROM/EEPROM chip with at least 8 address bits will do the job. Just put the following into its memory.

ADDR         VALUE
0b00000000   xxxxx000
0b00000001   xxxxx000
0b00000010   xxxxx000
0b00000011   xxxxx000
0b00000100   xxxxx000
0b00000101   xxxxx000
0b00000110   xxxxx000
0b00000111   xxxxx010
0b00001000   xxxxx000
0b00001001   xxxxx000
0b00001010   xxxxx000
0b00001011   xxxxx011
0b00001100   xxxxx000
0b00001101   xxxxx011
0b00001110   xxxxx011
0b00001111   xxxxx010
0b00010000   xxxxx000
0b00010001   xxxxx000
0b00010010   xxxxx000
0b00010011   xxxxx100
0b00010100   xxxxx000
0b00010101   xxxxx100
0b00010110   xxxxx100
0b00010111   xxxxx010
0b00011000   xxxxx000
0b00011001   xxxxx100
0b00011010   xxxxx100
0b00011011   xxxxx011
0b00011100   xxxxx100
0b00011101   xxxxx011
0b00011110   xxxxx011
0b00011111   xxxxx010
0b00100000   xxxxx000
0b00100001   xxxxx000
0b00100010   xxxxx000
0b00100011   xxxxx101
0b00100100   xxxxx000
0b00100101   xxxxx101
0b00100110   xxxxx101
0b00100111   xxxxx010
0b00101000   xxxxx000
0b00101001   xxxxx101
0b00101010   xxxxx101
0b00101011   xxxxx011
0b00101100   xxxxx101
0b00101101   xxxxx011
0b00101110   xxxxx011
0b00101111   xxxxx010
0b00110000   xxxxx000
0b00110001   xxxxx101
0b00110010   xxxxx101
0b00110011   xxxxx100
0b00110100   xxxxx101
0b00110101   xxxxx100
0b00110110   xxxxx100
0b00110111   xxxxx010
0b00111000   xxxxx101
0b00111001   xxxxx100
0b00111010   xxxxx100
0b00111011   xxxxx011
0b00111100   xxxxx100
0b00111101   xxxxx011
0b00111110   xxxxx011
0b00111111   xxxxx010
0b01000000   xxxxx000
0b01000001   xxxxx000
0b01000010   xxxxx000
0b01000011   xxxxx110
0b01000100   xxxxx000
0b01000101   xxxxx110
0b01000110   xxxxx110
0b01000111   xxxxx010
0b01001000   xxxxx000
0b01001001   xxxxx110
0b01001010   xxxxx110
0b01001011   xxxxx011
0b01001100   xxxxx110
0b01001101   xxxxx011
0b01001110   xxxxx011
0b01001111   xxxxx010
0b01010000   xxxxx000
0b01010001   xxxxx110
0b01010010   xxxxx110
0b01010011   xxxxx100
0b01010100   xxxxx110
0b01010101   xxxxx100
0b01010110   xxxxx100
0b01010111   xxxxx010
0b01011000   xxxxx110
0b01011001   xxxxx100
0b01011010   xxxxx100
0b01011011   xxxxx011
0b01011100   xxxxx100
0b01011101   xxxxx011
0b01011110   xxxxx011
0b01011111   xxxxx010
0b01100000   xxxxx000
0b01100001   xxxxx110
0b01100010   xxxxx110
0b01100011   xxxxx101
0b01100100   xxxxx110
0b01100101   xxxxx101
0b01100110   xxxxx101
0b01100111   xxxxx010
0b01101000   xxxxx110
0b01101001   xxxxx101
0b01101010   xxxxx101
0b01101011   xxxxx011
0b01101100   xxxxx101
0b01101101   xxxxx011
0b01101110   xxxxx011
0b01101111   xxxxx010
0b01110000   xxxxx110
0b01110001   xxxxx101
0b01110010   xxxxx101
0b01110011   xxxxx100
0b01110100   xxxxx101
0b01110101   xxxxx100
0b01110110   xxxxx100
0b01110111   xxxxx010
0b01111000   xxxxx101
0b01111001   xxxxx100
0b01111010   xxxxx100
0b01111011   xxxxx011
0b01111100   xxxxx100
0b01111101   xxxxx011
0b01111110   xxxxx011
0b01111111   xxxxx010
0b10000000   xxxxx000
0b10000001   xxxxx000
0b10000010   xxxxx000
0b10000011   xxxxx111
0b10000100   xxxxx000
0b10000101   xxxxx111
0b10000110   xxxxx111
0b10000111   xxxxx010
0b10001000   xxxxx000
0b10001001   xxxxx111
0b10001010   xxxxx111
0b10001011   xxxxx011
0b10001100   xxxxx111
0b10001101   xxxxx011
0b10001110   xxxxx011
0b10001111   xxxxx010
0b10010000   xxxxx000
0b10010001   xxxxx111
0b10010010   xxxxx111
0b10010011   xxxxx100
0b10010100   xxxxx111
0b10010101   xxxxx100
0b10010110   xxxxx100
0b10010111   xxxxx010
0b10011000   xxxxx111
0b10011001   xxxxx100
0b10011010   xxxxx100
0b10011011   xxxxx011
0b10011100   xxxxx100
0b10011101   xxxxx011
0b10011110   xxxxx011
0b10011111   xxxxx010
0b10100000   xxxxx000
0b10100001   xxxxx111
0b10100010   xxxxx111
0b10100011   xxxxx101
0b10100100   xxxxx111
0b10100101   xxxxx101
0b10100110   xxxxx101
0b10100111   xxxxx010
0b10101000   xxxxx111
0b10101001   xxxxx101
0b10101010   xxxxx101
0b10101011   xxxxx011
0b10101100   xxxxx101
0b10101101   xxxxx011
0b10101110   xxxxx011
0b10101111   xxxxx010
0b10110000   xxxxx111
0b10110001   xxxxx101
0b10110010   xxxxx101
0b10110011   xxxxx100
0b10110100   xxxxx101
0b10110101   xxxxx100
0b10110110   xxxxx100
0b10110111   xxxxx010
0b10111000   xxxxx101
0b10111001   xxxxx100
0b10111010   xxxxx100
0b10111011   xxxxx011
0b10111100   xxxxx100
0b10111101   xxxxx011
0b10111110   xxxxx011
0b10111111   xxxxx010
0b11000000   xxxxx000
0b11000001   xxxxx111
0b11000010   xxxxx111
0b11000011   xxxxx110
0b11000100   xxxxx111
0b11000101   xxxxx110
0b11000110   xxxxx110
0b11000111   xxxxx010
0b11001000   xxxxx111
0b11001001   xxxxx110
0b11001010   xxxxx110
0b11001011   xxxxx011
0b11001100   xxxxx110
0b11001101   xxxxx011
0b11001110   xxxxx011
0b11001111   xxxxx010
0b11010000   xxxxx111
0b11010001   xxxxx110
0b11010010   xxxxx110
0b11010011   xxxxx100
0b11010100   xxxxx110
0b11010101   xxxxx100
0b11010110   xxxxx100
0b11010111   xxxxx010
0b11011000   xxxxx110
0b11011001   xxxxx100
0b11011010   xxxxx100
0b11011011   xxxxx011
0b11011100   xxxxx100
0b11011101   xxxxx011
0b11011110   xxxxx011
0b11011111   xxxxx010
0b11100000   xxxxx111
0b11100001   xxxxx110
0b11100010   xxxxx110
0b11100011   xxxxx101
0b11100100   xxxxx110
0b11100101   xxxxx101
0b11100110   xxxxx101
0b11100111   xxxxx010
0b11101000   xxxxx110
0b11101001   xxxxx101
0b11101010   xxxxx101
0b11101011   xxxxx011
0b11101100   xxxxx101
0b11101101   xxxxx011
0b11101110   xxxxx011
0b11101111   xxxxx010
0b11110000   xxxxx110
0b11110001   xxxxx101
0b11110010   xxxxx101
0b11110011   xxxxx100
0b11110100   xxxxx101
0b11110101   xxxxx100
0b11110110   xxxxx100
0b11110111   xxxxx010
0b11111000   xxxxx101
0b11111001   xxxxx100
0b11111010   xxxxx100
0b11111011   xxxxx011
0b11111100   xxxxx100
0b11111101   xxxxx011
0b11111110   xxxxx011
0b11111111   xxxxx010

One option would would be...

  • AT27C512R-45PU
    • 64K x 8-bit OTP EEPROM.
    • Costs like $3.
    • Gives you the answer in 45ns.
    • With 16 input bits you can make two of this circuit using just one chip.
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    \$\begingroup\$ Very clever. I assume the OP is a student, since their top tag is homework, so this might annoy their professor. But definitely handy in terms of space, speed, power and cost. \$\endgroup\$ Commented Sep 25 at 18:16
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    \$\begingroup\$ This is better than "throw a microcontroller at it", which would be the typical commercial solution to such a problem. \$\endgroup\$ Commented Sep 25 at 20:09
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    \$\begingroup\$ @Fourier_Asker, this answer is a perfectly valid technical solution (one I considered too, see my early question comment) but your question was for to you to learn problem solving in digital logic design and this wouldn't do that. I'm not at all criticising this answerer, they've posted a good quality answer, just being mindful of the object of the exercise. \$\endgroup\$ Commented Sep 25 at 21:06
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    \$\begingroup\$ Beware that many ROMs are glitchy, in the sense that their outputs will often momentarily glitch when the inputs change, even when moving between two addresses that are different in only one bit where the programmed values for both addresses are the same. This isn't always a problem, but can catch people off guard. \$\endgroup\$ Commented Sep 26 at 13:48
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    \$\begingroup\$ But you only need a 256x4 bit ROM; a 27C512 is overkill. AM27S21 would do (eight bits address, four bits out)<rocelec.widen.net/view/pdf/uwlc2iy8dp/…>. The 27C512 takes 16 bits address and delivers eight bits out. \$\endgroup\$ Commented Sep 27 at 8:55
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It can all be done with combinatorial logic, no sequential elements.

Use a priority encoder to find the first 1. Its result produces a mask that's ANDed with the input to remove the first 1.

This masked input goes to a second copy of the circuit that does the same, using a priority encoder to remove the second 1 from the input and pass that to the third circuit.

A third priority encoder produces the result.

A 'result valid' flag can be produced by the third stage: if that stage's masked input is 00000000 then valid is 0 else valid is 1.

For analysis and reduction of the circuit in a separate exercise...

This whole combinatorial circuit could be designed in VHDL or Verilog then free vendor software tools used to simulate then synthesise it for an FPGA or CPLD. The synthesis report would then tell you how small the circuit could be collapsed down using the target device's LUTs. Quite a bit, I'd imagine.

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  • \$\begingroup\$ Priority encoder will give me the last '1' if so (The MSB), not the LSB one. About VHDL or verilog, we didn't really use this, we need to design a circuit of it. But nonetheless, 3 priority encoder seems huge for this, I never thought it will take that many logic gates,. 10110100 - Priority encoder will give 111 \$\endgroup\$ Commented Sep 25 at 11:42
  • \$\begingroup\$ @Fourier_Asker, A priority encoder will find the bits in the order you present them - just wire it up the right way around. \$\endgroup\$ Commented Sep 25 at 11:46
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    \$\begingroup\$ This! Any sequential logic circuit will take longer to get the answer. And handles changes to the input much better. \$\endgroup\$ Commented Sep 25 at 12:12
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    \$\begingroup\$ @periblepsis God lord, this is making me afraid, I was expected to do this? OMG I think I will try to understand it tommorow (its 23:38 to me right now), it seems huge Thanks!! \$\endgroup\$ Commented Sep 25 at 20:38
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    \$\begingroup\$ @periblepsis, it's better if I reply to OP comments to me myself. Since this is most likely a homework question, I provided an answer that gives guidance to a solution, putting the OP's education above enjoying myself rattling off a schematic . You instead chose to spell out a whole circuit, apparently failing to recognise and satisfy the point of the exercise. But in a circuit they can't build. Anyway, you can discuss your answer in comments on it there instead. \$\endgroup\$ Commented Sep 25 at 20:52
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There seems to be some debate about sequential vs combinatorial logic. Assuming sequential, you'll need to gate your clock.

The following is based on your question:

I know how to build a circuit that counts the number of 1s in an 8-bit input — it can be done using Full Adders and Half Adders. The problem is how to make it stop once it reaches three 1s, and then output a 1 at that exact moment or output 0 if it didn’t reach that count.

In the diagram, the clock will run as long as the adder output is not 11 (i.e. three 1's were found).

As an exercise to the OP, try to incorporate this to accommodate the when the MSB is reached without any 1's detected.

enter image description here

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  • \$\begingroup\$ Will try, Thanks. \$\endgroup\$ Commented Sep 25 at 12:09
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    \$\begingroup\$ I inferred you are a student, so I tried to teach you how to fish and not give you the fish. \$\endgroup\$ Commented Sep 26 at 11:36
  • \$\begingroup\$ Its all right :) \$\endgroup\$ Commented Sep 27 at 7:12
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Here is combinatorial solution I think is rather elegant and efficient. For brevity and clarity I have it in Verilog. It ought to be easy to translate into gates. Though, I did punt on the encoder by just writing the behavioral code, but that should be easy enough to translate also.

How it works is there are two stages which filter out the lsb bits up to the first 1. The filters work by masking, like how TonyM said. The first stage filters out the first lsb, second stage filters the second lsb, and the last stage simply needs to have the lsb position observed.

The trick with the filter operation was to think carefully about the mask conditions. I ended up making a truth table for the mask bit in terms of the previous two rows of A and the previous mask bit. I used a k-map to simplify.

In the end, the next mask bit was just the previous mask bit ORed with the previous A. If I was smarter then I could have just figured that out, but I'm not.

I think there is room for improvement by combining the two stages together and simplifying. Doing that would cause the first two mask bits to always be zero, for example. Also, I think that would reduce the depth of the logic (though, maybe not).

Here is the solution:

    // A[n-1], A[n], mask[n-1]  |  mask[n]
    // ---------------------------------------
    // 0 0 0 | 0
    // 0 0 1 | 1
    // 0 1 0 | 0
    // 0 1 1 | 1
    // 1 0 0 | 1
    // 1 0 1 | 1
    // 1 1 0 | 1
    // 1 1 1 | 1

    module filter_lsb(input [7:0] A, output [7:0] Q);
       wire [7:0] mask;
    
       assign mask[0] = 1'b0;
       assign mask[7:1] = mask[6:0] | A[6:0];
       assign Q = A & mask;
    endmodule
    
    module count_3rd_lsb(input [7:0] A, output logic [2:0] Q);
       wire [7:0] stage_1;
       wire [7:0] stage_2;
    
       filter_lsb f1(.A(A)      , .Q(stage_1));
       filter_lsb f2(.A(stage_1), .Q(stage_2));
    
       always_comb begin
          casex (stage_2)
             8'b0         : Q = 3'd0;
             8'bx1        : Q = 3'd0;
             8'bx10       : Q = 3'd1;
             8'bx100      : Q = 3'd2;
             8'bx1000     : Q = 3'd3;
             8'bx10000    : Q = 3'd4;
             8'bx100000   : Q = 3'd5;
             8'bx1000000  : Q = 3'd6;
             8'bx10000000 : Q = 3'd7;
          endcase
       end
    endmodule
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  • \$\begingroup\$ Hi, sadly I dont' know verilog much, I learnt the basics (Very basics) myself, but to turn a verilog code into circuit, its something people do usually courses like Logic synthesis. I am too "new" to learn such things. Thanks though! \$\endgroup\$ Commented Sep 25 at 20:46
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    \$\begingroup\$ There is an often repeated maxim from my generation: "Youu can doooo itttt!" This isn't anything too fancy, I promise. I'd say throw it into your favorite AI and ask it to explain the syntax, and you'll be off and rocking. \$\endgroup\$ Commented Sep 25 at 20:57
  • \$\begingroup\$ For emphasis: as shown in module count_3rd_lsb, module filter_lsb needs to be applied twice (implemented and wired twice) before priority encoding the result. \$\endgroup\$ Commented Sep 26 at 14:57
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For a sequential implementation, you just need a pair of counters that have "enable" inputs, and a small amount of additional logic.

schematic

simulate this circuit – Schematic created using CircuitLab

I've edited the circuit to add a missing gate (AND6). U1 counts the ones while U2 counts all the bits. U1 can be only 2 bits because it only needs to count to 3 (binary 11). U2 needs to be 4 bits because it needs to be able to count to 8 (see below). AND1 through AND4 force the output to zero if there aren't 3 ones in the data. This all pretty much follows from the problem description.

Note that this circuit outputs 3 through 8 for valid inputs (and zero otherwise). If you want 2 through 7, you'll have to subtract one, or figure out a way to inhibit U2 from counting the first bit.

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  • \$\begingroup\$ Very much thanks, if you can explain this I would be very much happy, I really cannot understand what is in here. Why choose 2bit counter or 4bit counter? What is the intuition behind this? I cannot understand how am I supposed to really think of that, I can understand why this question wasn't mandatory, but still, its annoying he thought I should solve this \$\endgroup\$ Commented Sep 25 at 20:44
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    \$\begingroup\$ See edit above. \$\endgroup\$ Commented Sep 25 at 23:18
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This circuit uses half adders to count high bits and or gates to copy the count one it reaches two and finally and gates to copy the remaining high bits down to the bottom.

schematic

simulate this circuit – Schematic created using CircuitLab

Feed the result from this to a priority encoder.

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  • \$\begingroup\$ Interesting actually, thanks :) \$\endgroup\$ Commented Sep 27 at 7:15
  • \$\begingroup\$ (There's an error at the A input of HA3: the input signal connects to HA2 S instead of skipping it.) \$\endgroup\$ Commented Sep 27 at 7:55
  • \$\begingroup\$ (I think you can substitute the XOr in the HAs by an OR.) \$\endgroup\$ Commented Sep 27 at 7:57
  • \$\begingroup\$ (This is beeflowbill's answer in schematic guise.) \$\endgroup\$ Commented Sep 27 at 8:00
  • \$\begingroup\$ Well at least is of use to those of us who cannot read verilog \$\endgroup\$ Commented Sep 27 at 8:24
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There are two very different behaviours called counter:

  • a sequential circuit where "clock" edges or pulses cause its state to change: The state represents information about the count of recent events. These can be "stopped", e.g. by not enabling the clock or inhibiting it.
  • a combinatorial circuit mapping some binary input signals into some numerical representation of the number of active inputs.
    As these "are not running", there's no stopping them - but on third take, you got me thinking:
    Manipulating the input signals such that a standard component produces the required result, can that component be a unary-to-binary encoder just as well as the (priority) encoder suggested more than once?

How to design a circuit …

Starting to state the obvious: there are about as many ways to design a circuit as there are to skin a cat.
The way to meet somewhat involved requirements without readily available (partial) solutions is to use something programmable - even more handy where requirements may change.

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