0
\$\begingroup\$

Are there logic-level chipsets where the signals can be inverted or non-inverted with a common control pin? For example, a quad input/quad output IC with a common control pin where the outputs are non-inverted when said common control pin is held low, and then the outputs are inverted when the common control pin is held high?

XOR gates seem like the obvious solution, but I have had limited success. I am also familiar with/aware of ICs in the 74XX family that have three-state outputs, but those don't quite address what I am looking for, and I have not come across a suitable solution despite my searching, so I am curious if there are any additional options to entertain?

\$\endgroup\$
6
  • \$\begingroup\$ Sounds like an XOR function. (Or XNOR.) Would a quad XOR suffice? \$\endgroup\$ Commented Jan 14 at 23:14
  • \$\begingroup\$ You tried this where? on a FET bridge with shootthru? \$\endgroup\$ Commented Jan 15 at 1:25
  • 4
    \$\begingroup\$ Without seeing layout, waveforms, and timing constraints (datasheets, and waveforms to confirm it), we cannot tell why you've met with limited success. As comments have noted, your question clearly defines an array of XOR gates. If the chip(s) you have are indeed XOR gates, and the XOR function is what you require, then the problem must lie elsewhere. \$\endgroup\$ Commented Jan 15 at 1:27
  • \$\begingroup\$ In my experience, 74xx86 XOR gates are pretty glitchy: they can toggle off and on a few times before settling to the right logical value, due to multiple internal propagation delay paths within each XOR gate. So using XOR gates might work, as long as the outputs go into some flip-flops to properly synchronize everything, after allowing enough propagation delay. I would definitely not use XOR gates on any edge-sensitive timing signals due to the inherent glitchy-ness. The best alternative that springs to my mind is an array of MUX+FF based LUT's, i.e an FPGA. Those aren't DIP-friendly though. \$\endgroup\$ Commented Jan 15 at 3:15
  • 1
    \$\begingroup\$ Probably not if you're going into a memory with bus signals not delayed respectively. If you can insert another wait state, perhaps (if it's on the right phase and everything) -- but again -- without timing diagrams, datasheets, application in general, we cannot know. \$\endgroup\$ Commented Jan 15 at 9:52

1 Answer 1

Reset to default
2
\$\begingroup\$

It sounds like what you want is an exclusive-or gate. The 74xx86 family of chips contain 4 exclusive or gates. You can tie one of the inputs on each gate together to make all the gates invert or not invert simultaneously.

\$\endgroup\$
4
  • \$\begingroup\$ I appreciate the answer! I have actually tried XOR gates before (and have asked recently about them), but I seem to be having issues with the common gate line not working as intended, so I wondered if there was another solution that I might have been missing. \$\endgroup\$ Commented Jan 14 at 23:18
  • 3
    \$\begingroup\$ @paraparabolic, that comment makes this read like an X-Y problem to me. Taking a step back, please edit your question to explain what the larger circuit is that you're trying to design. \$\endgroup\$ Commented Jan 14 at 23:30
  • 7
    \$\begingroup\$ @paraparabolic - if an XOR gate did not work for you there was problem in your implementation or you are not describing the problem correctly. \$\endgroup\$ Commented Jan 14 at 23:58
  • \$\begingroup\$ The point is to drive one input of each the four xor gates with a common signal. What issues you experienced and why it would be any different to drive one or multiple inputs with the signal that controls the inversion? \$\endgroup\$ Commented Jan 15 at 8:04

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.