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This is from the datasheet for the TPS786 LDO:

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I am trying to understand how the SHUTDOWN' input to the error amplifier causes shutdown mode. The datasheet says:

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My understanding is that when EN is low, it causes SHUTDOWN' to go low, cutting off the output current. But what I can't figure out is what exactly would the SHUTDOWN' input go into in the error amplifier? In order to cut off the output current, you would want VSG < Vth, so you would want VG to go high for shutdown mode. Does the SHUTDOWN' input cause the error amplifier output (VG) to shoot up to the positive rail?

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    \$\begingroup\$ Yes, there will be a pullup \$\endgroup\$ Commented Nov 27, 2024 at 0:31

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The datasheet says that current in shutdown mode is 70nA, which is really low. To achieve that, many elements inside the regulator IC must be be disabled, not only the output.

For instance, the 1.25V reference needs to have its own current source cut off, to prevent it drawing current from the input. The UVLO system no doubt uses a resistor divider and comparator to do its job, both of which require current to operate, and that system would need to have its power supply cut off too.

In shutdown mode, to switch off the pass MOSFET, its gate must have the same potential as \$V_{IN}\$, so that \$V_{GS}=V_G - V_S = 0V\$. Therefore, in shutdown mode the error amplifier output needs to be \$V_G = V_S = V_{IN}\$.

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Yes, there should be a passive Vg pullup to Vs for SHUTDOWN ="0'

How it is implemented with BiMOS technology is not described but has a low shutdown current for FET switches being rated at 0.07 nom. to 1 uA. Open collector might be a lower current method of gate driving for low current.

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