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I want to simulate the principle of 1T1C DRAM cell. But if I model voltage source in Bit line, bit-line voltage is set by its input signal. So I want to seperate bit line, using ideal MOSFET component, but I cannot find ideal MOSFET model.

Question List

  1. Is there any ideal MOSFET model in LTspice?
  2. I want to know the way how set voltage in a node.

following is my circuit. enter image description here

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  • \$\begingroup\$ An ideal mosfet is modeled as: if Vgs > Vth then Id = Vds/Rdson else Id = Vds*Goff. Or something like that. Just create a model. You set a node voltage by either tying a grounded voltage source to it (sure-fire way) or else you use the .IC card and specify it for the start of a run (but it will change over time during the .TRAN.) \$\endgroup\$ Commented Apr 19, 2024 at 5:52
  • \$\begingroup\$ Probably best to use the voltage-controlled switch for something like this. The symbol is named sw and you need to put a SPICE directive on the schematic for the .model ... statement. See the help page I linked for more info. You should try to use something like Roff=1t or higher to minimize leakage when the MOSFET is off (t = tera or 1e12). \$\endgroup\$ Commented Apr 19, 2024 at 7:26

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