Error 10170 in SystemVerilog for adder

Question

I'm trying to build an n_bit adder, but the Quartus gives me this error:

Error (10170): Verilog HDL syntax error at n_bit_adder.sv(12) near text: "for"; expecting "endmodule". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Line 13 is the like where the for is used.

module n_bit_adder #(parameter N = 4)(
    input logic [N-1] a,
    input logic [N-1] b,
    input logic cin,
    output logic [N-1] s,
    output logic cout
);

    logic [N-1:0] carry;
    assign carry[0] = cin;
    
    for (i = 0; i < N; i = i + 1) begin
        fullAdder f0 (.A(a[i]), .B(b[i]), .Cin(carry[i]), .Cout(carry[i+1]), .S(s[i]));
    end
endmodule

module fullAdder
(input logic A,
 input logic B,
 input logic Cin,
 output logic Cout, 
 output logic S
 );
    assign S = A ^ B ^ Cin;
    assign C = (A & B) | (A & Cin) | (B & Cin);

 endmodule

toolic · Accepted Answer · 2024-02-26 12:21:40Z

When I compile your code with the Synopsys VCS simulator, I get a more helpful error message:

Identifier 'i' has not been declared yet.

This is for the line:

for (i = 0; i < N; i = i + 1) begin

All identifiers must be declared. Since this for loop is used as a generate construct, you must declare i as a genvar. For example:

for (genvar i = 0; i < N; i = i + 1) begin

Refer to IEEE Std 1800-2017, section 27. Generate constructs

After I fix that, there are more compile errors due to how you declared your vector signals. The following compiles without errors on multiple simulators:

module n_bit_adder #(parameter N = 4)(
    input logic [N-1:0] a,
    input logic [N-1:0] b,
    input logic cin,
    output logic [N-1:0] s,
    output logic cout
);

    logic [N:0] carry;
    assign carry[0] = cin;
    
    for (genvar i = 0; i < N; i = i + 1) begin
        fullAdder f0 (.A(a[i]), .B(b[i]), .Cin(carry[i]), .Cout(carry[i+1]), .S(s[i]));
    end
endmodule

You must review this carefully to make sure it is the logic you are trying to design.

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