I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2). each BO has different impedance and length consideration. what's the reason behind this? why there is no straight line from Via 1 to Via 2 through the M (Main Trace) segment?
The first BO1 is probably the trace and or processor pin impedance (make sure you include the package trace length in DDR4 calculations if the device package is not length matched). The BO2 could be related to the via, although normal routing (I would think) that the trace size or impedance would not chanage so BO2 should be the same as M unless it has something to do with the via or you are changing trace sizes in a BGA fanout.
