1
\$\begingroup\$

To drive a RLC circuit by pulsing at a frequency close to 1MHz, I would like to use a schmitt trigger inverter gate (SN74AC14) / buffer (SN74LVC2G17) in between the uC pin and RLC circuit for higher current output (50mA). Since, they have a voltage drop at pins at their maximum current output. I was wondering, if I could reduce the drop by combining two output gates powered by single input.

RLC circuit driven by two Inverter outputs combined

Of course, I could foresee that there will be a short circuit involved during mismatch of the gates during the transition phases of the inverter / buffer circuit. But since they are from the same chip, I was having the feeling that the would have very similar switching / propagation characteristics and even if they mismatch, that would be for a very short time (<10ns?)

My questions are: (1) Is this mismatch negligible meaning would the thermal model allow this short circuit for small time at a frequency 1MHz? (2) Would this configuration still reduce the voltage drop on my output without compromising the max. limits of the component? (3) Is there other consequences that I have missed?

Thanks!

\$\endgroup\$
5
  • 1
    \$\begingroup\$ Why not move the resistor to the gate outputs then, split it into two resistors that each gate feeds individually? \$\endgroup\$ Commented Nov 13, 2019 at 10:16
  • \$\begingroup\$ @Andyaka Thanks for your suggestion. Yes, that is a possibility. But I have placed this resistor to monitor the resonance condition of the RLC circuit by measuring the drop. Moving it next to the inverter would compromise this function. Additionally, I can split the resistors (one next to inverter and one next to ground) but then that would increase my footprint. \$\endgroup\$ Commented Nov 13, 2019 at 10:38
  • \$\begingroup\$ If your input has a nice sharp edge, you shouldn't have a problem. I wouldn't design a product like this, but it looks like you're doing a lab measurement. If you don't have a nice sharp edge on the input, buffer it with a third Schmitt trigger. \$\endgroup\$ Commented Nov 13, 2019 at 21:23
  • \$\begingroup\$ Hello Cristobol, Thanks for your comment. I am looking for alternatives for a demo but I do want to reproduce it, if needed. The input is from a microcontroller pin coupled to its oscillator which has a maximum rise/fall time of 15ns. I thought it is fast enough. What are your thoughts? Do you have other alternatives in mind? \$\endgroup\$ Commented Nov 14, 2019 at 8:07
  • \$\begingroup\$ [FAQ] Can I connect two outputs from a CMOS logic device together directly? \$\endgroup\$ Commented Nov 14, 2019 at 8:24

2 Answers 2

Reset to default
1
\$\begingroup\$

If you have (need) Schmitt triggers, then combining them is not ideal.

Schmitt triggers are used when the input slew rate is slow; it is possible that the two inputs have different thresholds, or that noise coupling between the two circuits causes one to trip before the other. This will create a conflict at the output where the two circuits conflict. In the worst case, you could get multiple transitions at the output even if there is only one (slow) transition at the input.

\$\endgroup\$
0
\$\begingroup\$

I have paralleled CMOS gates frequently, up to eight in one package, and never blown out the IC. It is best to use non-inverters though; inverters can produce a burst of high frequency oscillations on each transition. Some AC buffers have more sinking capability than sourcing and this might affect your test.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.