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The 2-phase dual-rail protocol in the concept of asynchronous handshaking relies on detecting signal transitions.

How do we detect a signal transition from LOW to High or HIGH to LOW? What is the output of this detection? A permanent High? or LOW? or another transition?

I need the transistor level schematic or at least a few words on the design concept to help me come up with the design by myself.

My initial thought is to put a memory element on the signal and then after the transition happens we can compare the signal with previous value and detect a change, but then how do we detect the transition itself?

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    \$\begingroup\$ Typically, microcontrollers allow to raise an interrupt when the signal at a GPIO pin changes. But you did not say anything about the context. Do you have an actual problem you're trying to solve, or is this a homework question? \$\endgroup\$ Commented Jun 14, 2016 at 9:06
  • \$\begingroup\$ It is not a homework. I am researching asynchronous circuits as a PhD student. Mentioning micro-controller was useful, thanks. At least can go to their datasheets and see how they detect the change. But I guess there will be no transistor level schematic or detailed explanation. The context is just the first line. \$\endgroup\$ Commented Jun 14, 2016 at 9:25
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    \$\begingroup\$ For information, in the digital, synchronous world (MCU/FPGA), the way to detect a change is to sample the value at each clock (taking care of metastability), and comparing the sampled value with the previous one (that you memorized in a flipflop). But you won't see this described in details in the MCU datasheets, it would be like describing how CPU registers are implemented. You will however be able to find FPGA development tutorials that describe this method. \$\endgroup\$ Commented Jun 14, 2016 at 11:58
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    \$\begingroup\$ In the context of asynchronous design, start with the "Muller C-element". But async design is a dead end anyway. \$\endgroup\$ Commented Jun 14, 2016 at 12:57

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You're on the right track with your idea of putting a memory element on the signal etc.

Since a D flip-flop is a basic element of acting upon a transitions it helps when you look at how it is implemented

by a bunch of NAND gates.

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  • \$\begingroup\$ Thanks, but seems both of them act open only the positive edge. I guess to capture at both edges we must copy the design and make it negative edge sensitive. That is way too much overhead. \$\endgroup\$ Commented Jun 14, 2016 at 10:19
  • \$\begingroup\$ There must be another way. \$\endgroup\$ Commented Jun 14, 2016 at 10:19
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    \$\begingroup\$ Yes, they both work on positive edges only, but of course can be done the other way round too (or just add an inverter in front). \$\endgroup\$ Commented Jun 14, 2016 at 10:28
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    \$\begingroup\$ You asked for the "standard way". That's it. If you think this is "way too much overhead" you should tell at least something about your requirements. Maybe you could use some dynamic designs using capacitors but if you want to go that way you have to tell much more about your general conditions (e.g. rise/fall times). \$\endgroup\$ Commented Jun 14, 2016 at 10:34
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    \$\begingroup\$ I don't see the transition sensitivity in the capture/pass latch. It's level sensitive (that's why it is called a latch). Of course it surely could be used too to form some kind of transition sensitve storge element together with some other gates. \$\endgroup\$ Commented Jun 14, 2016 at 15:06
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The classic approach to this problem when dealing with digital logic is to use a single 2-input exclusive OR gate. Feed the signal directly to one input and through an RC delay to the other input. When the signal changes from low to high, the XOR gate will give an immediate output because only one of its two inputs is high. Shortly after that the second output will go high, thanks to the RC circuit, and that will cancel the XOR output. The result is a pulse out when the monitored signal changes from low to high. When the signal changes from high to low, the same sequence occurs, so the final result is a pulse when either a high-to-low or low-to-high transition occurs.

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You detect transitions using asynchroous state machines. A D flip-flop is just one example of an asynchronous state machine that happens to be very useful for building much larger synchronous state machines.

If you want to build asynchronous sequential logic in general, you'll have to define some basic building blocks that accept two (or more) sets of 2-rail dual-phase inputs and produce a 2-rail dual-phase output. A building block would like this would be an asynchronous state machine with 5 inputs and 3 outputs — much more complicated than a DFF, but still using the same design techniques internally.

It would seem that design techniques for generic asychronous state machines are not widely taught any more — 40 years ago, it ws a required part of an EE undergraduate curriculum. These days, nearly all sequential logic of any complexity is implemented with synchronous logic, and that's all that is taught. So you'll have to do some digging in order to get up to speed on this topic if this is something you want to pursue. It's a topic that's too broad to address in the Q&A format used here.

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  • \$\begingroup\$ "accept two (or more) sets of 2-rail dual-phase inputs and produce a 2-rail dual-phase output" this is EXACTLY what I am aiming to solve. \$\endgroup\$ Commented Jun 14, 2016 at 15:03
  • \$\begingroup\$ I think the output no need to be a 2-rail dual phase. It can be level logic being fed into a Muller gate. \$\endgroup\$ Commented Jun 14, 2016 at 15:04
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You can use the following schematics with 2 D Flip-Flops and an XOR gate:

Transition detector

q1 is the value of J delayed 1 clock cycle and q2 is the value of J delayed 2 clock cycles. When you XOR q1 and q2, you basically compare the values of J that differ in time by one clock cycle. When q1 != q2 (transition), XOR output = "1". When q1 = q2 (the signal remains the same), XOR output = "0". Hence, you detect the transitions (both "1 -> 0" and "0 -> 1") of your input signal J.

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  • \$\begingroup\$ The image was created by myself. \$\endgroup\$ Commented Nov 5, 2021 at 18:03

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