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euraad
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Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Update:

This is one example where I add a copper plane and asign VDD onto it. Now the stack is

Signal/GND GND GND Signal/GND

Perhaps this is not good at all? I need to get the capacitor-effect? The C144 is a 10 uF capacitor.

enter image description here

If I cover the second layer with the first layer like this.

enter image description here

Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Update:

This is one example where I add a copper plane and asign VDD onto it. Now the stack is

Signal/GND GND GND Signal/GND

Perhaps this is not good at all? I need to get the capacitor-effect?

enter image description here

Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Update:

This is one example where I add a copper plane and asign VDD onto it. Now the stack is

Signal/GND GND GND Signal/GND

Perhaps this is not good at all? I need to get the capacitor-effect? The C144 is a 10 uF capacitor.

enter image description here

If I cover the second layer with the first layer like this.

enter image description here

added 179 characters in body
Source Link
euraad
  • 1.5k
  • 21
  • 45

Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Update:

This is one example where I add a copper plane and asign VDD onto it. Now the stack is

Signal/GND GND GND Signal/GND

Perhaps this is not good at all? I need to get the capacitor-effect?

enter image description here

Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?

Update:

This is one example where I add a copper plane and asign VDD onto it. Now the stack is

Signal/GND GND GND Signal/GND

Perhaps this is not good at all? I need to get the capacitor-effect?

enter image description here

Source Link
euraad
  • 1.5k
  • 21
  • 45

Should reference plane change its potential value if a track goes to another layer?

Assume you have a four layer board.

  1. Signal
  2. GND
  • Dielectric
  1. VDD
  2. Signal

And you having a track in the 4:th layer. Suddenly you're using a via to go through the 4:th layer to 1:st layer.

Question

The reference plane for the 4:th layer is the 3:rd plane, which has a potential lager than GND volt. The VDD don't have to be 3V3 volt, it can be voltage for DDR memory as well.

But once you're routing your track from 4:th layer to 1:st, you're also changing the reference plane to GND, which is now 2:nd layer.

Should you place a copper plane at the 2:nd layer which has the same voltage potential as the 3:rd layer?